OEMs to EDA world: Time to catch up

Warnings of such a shift became public earlier this month at the International Symposium on Physical Design (ISPD), when Gary Smith, chief EDA analyst at Gartner Dataquest, said that 27 percent of engineers are now using in-house EDA tools. That's up from 20 percent in 2001 but down from 28 percent in 2000.

Major electronics OEMs differ on their use of internal tools. But they don't hesitate to complain about unmet needs, particularly in two areas: tools for system-level design and tools that analyze deep-submicron effects, including design-for-manufacturability (DFM).

"I don't sense that, with us or our customers, there's any difference in spending," said Richard Tobias, vice president of the ASIC and foundry business unit at Toshiba America Electronic Components. "But where there are no tools available, you develop tools. And there are areas in which tools are not available."

In his ISPD talk, Smith said that a lack of 65- and 45-nanometer design tools is driving many electronics companies to build their own. "The problem since 2000 is that we haven't been getting the tools in time," he said. "OEMs would rather buy tools from EDA companies, but when they don't exist, they build them in-house."

One area that appears to be crying out for solutions is electronic system-level (ESL) design. In separate keynotes at the recent Electronic Design Processes workshop, speakers from IBM and Intel stressed the need for better offerings.

John Darringer, manager for system-level design at IBM Corp.'s Thomas J. Watson Research Center, noted that electronic design typically starts with spreadsheets. Then people build technology models for power, timing and yield, along with performance models for cores, caches, buses and memories. But they don't talk to one another. And then there's a "vague handoff" to RTL. "I need a way to bring these models together," he said.

Gadi Singer, general manager of Intel Corp.'s low-power IA and technology group, called on the EDA industry to step up from single-chip solutions to "platform-oriented design." A platform, in Singer's view, might include multiple chips and embedded software. Supporting that requires high-level modeling and hardware/software co-design, he said.

Darringer said IBM has always done chip design using mostly internal tools, and that model is not changing much. At Intel, Singer said, processor design is mostly based on internal tools, while the communications products and chip sets are mostly designed with commercial EDA tools.

"I don't see any major shift," Singer said. "I'd say there's a similar balance between internal and external tools." But he quickly added, "We really need to get to a higher level so we can deal with platforms."

Going inside
One company moving more toward internal EDA tools is Texas Instruments Inc., where current usage of internal tools is at about 15 percent, said Mike Fazeli, worldwide EDA strategies manager. "TI's needs are ahead of industry offerings by 18 to 24 months," he said.

Fazeli said TI develops and uses internal tools, including a Spice simulator, specialized placers and routers, power management tools, verification management tools and system-on-chip integration tools. "Semiconductor vendors cannot wait for an EDA tool market to develop and hence are having to develop internal leading-edge tools," he said.

EDA vendors need to strengthen their efforts in power management, DFM-aware physical verification, statistical analysis, coverage-driven functional verification, static and semiformal checkers, hardware/software co-design and embedded-software development platforms, Fazeli said. He said TI's internal tool budget was "slightly on the rise."

About 20 percent of the tools at Philips Semiconductors are internal, said Lambert van den Hoven, vice president and general manager of the design technology group. He said EDA vendors are not meeting several needs, including high-level synthesis and design exploration, deep-submicron modeling for signal integrity and substrate noise, electrical and thermal tools for packaging and DFM, yield and reliability. In some areas, he noted, startups are offering solutions.

But others are not increasing internal tool development. "Clearly, for ST, the trend is to rely more and more on external tools," said Philippe Magarshack, central R&D group vice president for design automation and libraries at STMicroelectronics. But he said that since some of the tools and features are not available from big EDA vendors, ST is working with small providers and startups.

Nor is National Semiconductor Corp. increasing its use of internal tools, said James Lin, vice president of technology infrastructure. Only smaller CAD utilities, such as a library characterization tool, are done internally, he said.

Catching up is key to the EDA industry's success, said Dataquest's Smith. "If the EDA industry provides tools on time, it will continue to be a growing market," he said. "If not, the tools will increasingly be built in-house by the semiconductor vendors."