Mesa, AZ., April 28, 2005 – Tallika Corporation, an Intellectual Property and Design Services Company, today disclosed that it has been shipping DDR I/II Controller Core to beta customers.
Tallika’s DDR Controller has been verified using a completely pseudo-random self-checking Verification environment to validate interoperability with the industry’s leading DRAM Manufacturers. Deliverables include Verilog RTL, Reference Physical Implementation, Static Timing Scripts, and Verification Environment.
“Tallika is committed to providing leading edge complete IP solutions to enable our Customers to get to Market faster,” said Hemi Bhatnagar, President, CEO of Tallika Corporation. “Our ability to engage with customers early on at an architecture level, create and provide a best fit Custom IP Core solution, and then complement the solution with best-in-class implementation services/reference implementation, enables us to provide low-risk high-value solutions to our customers in a broad array of market segments”.
- Innovative Application side interface for easy integration
- Supports DDR I and II Jedec standards
- Programmable timing parameters
- Supports DDR with 4 and 8 banks active
- Configurable Command and Data queue depths
- Supportd data rates upto 666 MHz in DDR2
- Supports x4, x8 and x16 parts from all major memory manufacturers
- Optional support for ECC
- User Selectable Word Widths
- Verified with industry leading IO partners to provide a complete solution
About Tallika Corporation
Tallika Corporation is a leading provider of Silicon Intellectual Property and Professional Services for consumer, networking, computing, and storage markets.
For more information on Tallika’s Products and Services, please visit http://www.tallika.com