By John Weekley, Synopsys Inc. -- 3/30/2005
The 2003 International Technology Roadmap for Semiconductors (ITRS) projects that 75 percent of design productivity improvement will come from IP reuse and 25 percent from improved EDA tools, flow, or methodologies. The newest roadmap calls for widespread reuse of IP blocks greater than 1 million gates. These so called "very large blocks" are being implemented as templates, subsystems or platforms and not as a collection of individual cores. It would seem that IP reuse is now the key factor in design economics.
Using market forecasts for ASIC and ASSP design starts with process technology and the ITRS assumptions about increased IP block reuse, there will need to be 100 billion gates of re-used logic blocks in 2007's design starts. That would be 10 thousand blocks of million-gate size, re-used logic blocks.
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