LONDON PicoTurbo Inc. (Milpitas, Calif.), a developer of ARM-compatible intellectual property (IP) cores, plans to announce an ARM9-like core at the IP-based Design conference and exhibition, which opens Thursday (Dec. 14) in Grenoble, France.
PicoTurbo, which announced a series of ARM-compatible 32-bit processor cores earlier this year, is being sued by ARM Ltd. (Cambridge, England) for alleged patent infringement. Undaunted, an executive of PicoTurbo is due to attend the two-day conference and to unveil the PT-110-AX, an ARM9E-like enhancement of PicoTurbo's previously announced PT-110.
PicoTurbo pitches the PT-110, which can run the ARM version4T instructions and has a dedicated multiplier, as an ARM9E replacement. The latest AX version has additional instruction and data scratch-pad memories that allow the processor to store critical subroutines in local memory so that they can be run without t he latency of external memory. This feature is included to speed up certain DSP-intensive embedded applications, the company said.
The PT-110-AX also includes an instruction pre-fetch cycle, a cache lock for critical real-time operations, programmable write-back and write-through, an Amba bus interface and a separate coprocessor interface.
"The design is complete, were doing final verification and we're due to tape out in January," said Bruno Kajiyama, vice president of marketing at PicoTurbo.
With design of the core targeted at 0.18-micron CMOS production, the PT-110-AX occupies 1.9 square millimeter of silicon, is expected to run at clock frequencies up to 300 MHz and to consume about 0.7 milliwatts per MHz.
"The PT-110 already had a memory management unit and instruction and data caches. In this enhancement we're adding tightly-coupled memory sort of level-zero caches of 2 kbytes," said Kajiyama.
For licensees, the final size of the scratch-pad memories is negotiable, Kajiyama said, and the performance enhancement it brings will depend on the application. "There are tightly-looped routines in some DSP problems. So, for instance, in codec applications this can make a difference. A software modem would be a good example."
PicoTurbo's coprocessor interface allows licensees to add their own logic in the form of a hardware engine to accelerate algorithms still further. The PT-110-AX core also includes full scan with test coverage up to 97.8 percent, the company said, and retains the ability of the PT-110 to be piggybacked onto standard ARM development boards.
PicoTurbo has chosen to build-in an Amba-style bus interface on the AX version. As Amba is an ARM-developed standard, PicoTurbo has chosen to implement a separate, proprietary coprocessor interface.
"Right now we don't have any peripherals," Kajiyama said. "This way licensees could get processor cores from us and peripherals from ARM and third parties."
PicoTurbo's cores have been well received this past year, an d Kajiyama said he expects the PT-110-AX to follow that lead. "We have 19 licensed cores so far for such applications as Bluetooth, MP3 players, an MP3 recorder, cellular telephones, a DVD player and networking applications, with customers in Taiwan and the U.S.," he said.
PicoTurbo is working with its early licensees and customers to build a marketing and technical support network, but Kajiyama declined to identify those parties. "We are trying to establish and manage the formal direction of the network, but it will be around the customers' IP and our IP working together," he said.
None of PicoTurbo's licensees has yet gone to market, but one customer is due to start volume production in the first quarter of 2001, about a year after signing a license agreement, Kajiyama said.
IP-based Design is organized by Institut National Polytechnique de Grenoble (INPG) and Design and Reuse (Grenoble, France). Gabriele Saucier, director of t he computer science laboratory at INPG, is chief executive of Design and Reuse. CMP Media Inc., publisher of EE Times, holds a 19 percent stake in Design and Reuse.