MANHASSET, N.Y. Intel Corp. and Analog Devices Inc. (ADI) this week rolled out the much-anticipated fruit of their 21-month collaboration, claiming their Micro Signal Architecture processor core goes beyond today's digital signal processors in merging DSP and microcontroller features to handle the demands of upcoming wireless systems.
But the companies provided little technical meat to support their claims (See also "Intel and ADI unveil joint DSP architecture" for more information). Indeed, the core is already coming under fire for allegedly delivering essentially what's already present in existing DSPs. The partners also may face an uphill battle in attracting third-party software support for a new instruction set in a crowded field.
Today's DSPs are ill-equipped to handle the high data rates and emerging multimedia traffic on 2.5- and third-generation wireless systems, said Analo g Devices' chief executive, Jerry Fishman. "Feedback from our customers has told us that current-generation DSPs are not satisfying their needs, and they can't be upgraded to do so."
That's why the two companies joined forces "to realize a new DSP architecture that could meet the new demands," Fishman said.
The Micro Signal Architecture includes multimedia extensions and performance primitives designed to speed the processing of audio, video, image and voice signals, along with dynamic power management to extend the battery life of portable systems. Additionally, the core combines frequency scaling and voltage scaling, a scheme said to up battery life by varying power consumption according to the demands of the application.
However, the lack of any real performance details or hard specifications makes it unclear how the core compares with established DSPs such as Texas Instruments Inc.'s C55x and the StarCore SC140 from the two-year-old Lucent and Motorola joint venture. Both of these offerings p ack features similar to those of the Micro Signal Architecture. Techniques like frequency scaling and dynamic power management are already widely used, analysts and observers said.
"Making aggressive claims on performance, without details, leaves a little bit of a sense that they're playing catch-up," said Jeff Bier, general manager of DSP research firm Berkeley Design Technology Inc. (Berkeley, Calif.). "And the lack of numbers supports this. Either they don't know, or they don't think [the figures are] particularly good."
"Until detailed performance descriptives become available, it's all just buzz words," said Paul Marino, director of Motorola's DSP Core Technology Center.
The new core will initially be available at 300 MHz and 600 million multiply-accumulate operations (336 Mips) on an 0.18-micron process. The architecture can be extended to more than 1 GHz and 2,000 Mips, said Ron Smith, president and general manager of Intel's Wireless Communications and Computing Group, all while operatin g at about 1 volt.
Products based on the core will appear separately from ADI and Intel "sometime in 2001," said ADI chief executive Fishman.
However, some in the industry questioned that road map. Intel and ADI canceled a planned discussion of their architecture at this year's Embedded Processor Forum, leading to questions about availability, and the lack of hard details at last week's announcement in New York underscored those concerns. ADI was "significantly late" in delivering both its Hammerhead and TigerSharc DSPs, said analyst Bier, "and TigerSharc was significantly under performance predictions. So, maybe they're being cautious [this time]."
At its initial 300-MHz speed, the new core will match the currently shipping StarCore SC140. TI's C55x is now shipping at 160 MHz, but "we'll be shipping 200 MHz by [the first quarter of] next year and 300 MHz by midyear," said Mark Mattson, worldwide C5000 product manager at TI.
The core consists of two multiply-accumulate units (MACs), two ar ithmetic logic units (ALUs) and shifter functions. Each MAC is capable of performing a 16-bit x 16-bit multiply in every cycle, with accumulation to a 40-bit result. The dual 40-bit ALUs operate on 8-, 16-, 32- or 40-bit data. The architecture can be scaled up or down to include more or fewer MACs and ALUs, said Smith.
The Micro Signal Architecture has a set of data and pointer registers for dealing with RISC-type instructions. "Any instruction can operate on any of the registers, there are no specific tie-ins from instruction and register," said ADI DSP architect Aaron Bauch. While running control instructions, both data and address registers are 32-bit registers. "So it looks very much like a 32-bit RISC with 32-bit addresses with a flat 4-Gbyte address space," Bauch said.
For DSP control instructions, "the user can feed any upper or lower 16-bit value into any other MAC, giving flexibility in where you feed data from and to," he said. "So for various algorithms, programmers have pretty much the da ta path they need.
"We're talking a clean-sheet architecture here, with all the orthogonality and programming model of a standard RISC instruction set," Bauch continued. "But integrated into that instruction set you also have the DSP capability and hardware of a best-in-class, dual-MAC 16-bit DSP without compromises on either side. There's no need for code partitioning, message passing or data sharing, thereby eliminating very complex structures."
Bauch also pointed to the Linux port. "This shows it's not your classic DSP architecture," he said. "It is one that can run robust, complex system code and at the same time gives you all the DSP capability that you need."
Intel and ADI have marshalled software support for the new architecture. Third-party developers to date include CMX Systems, Eonic, Hellosoft, Hitex Development Tools, Lineo and Realogy. Information is available at the Joint Development Web site.
Performance and architectural elegance may not be enough to establish the new part, however. The real problem, said analyst Strauss, is dislodging long-term relationships like TI's with Nokia and Ericsson. Nokia, for example, designs its own chips using TI's cores. "They're joined at the hip," Strauss said.
To date, no OEM partnerships stemming from the Intel-ADI alliance have been announced.
One potential advantage for ADI and Intel is that the TI parts are single-sourced, said Bier at Berkeley Design. "Customers don't want to get locked into one vendor," Bier said. "With Intel and ADI, there could potentially be multiple sources, although it's hard to see what their respective marketing strategies will be and who will be their customers."
Fishman said ADI will pursue the general-purpose DSP market, using the new core as its flagship in the 16-bit arena. Intel will favor applications in line with its StrongARM processor family as part of the company's Personal Internet Client Architectu re.
Another advantage claimed by the two companies is C/C++ programming. "Up to 80 percent of code developed for the Micro Signal Architecture can be done in C/C++," Intel's Smith said. "This speeds time-to-market and widens the potential pool of developers, thereby making more code available."
Nonetheless, said analyst Bier, "designers still can't easily migrate their existing assembly-language code from existing ADI processors, or for that matter from earlier processors from other vendors. For TI's C55x, on the other hand, [migration] was never an issue, since it's code-compatible with the whole C5000 platform."
TI's Mattson questioned ADI's ability to support yet another line of DSPs. "How can they support Sharc and TigerSharc, which are incompatible on the floating-point side, and the 218x and 9x, which are incompatible with the new Micro Signal Architecture?" he asked. "They will have a lot of architectures to support. The customer response will be interesting." The C/C++ programmability wi ll help, but "that still leaves 20 percent in assembly, and that's not going to be able to be ported over," said Mattson.
For mobile applications, few benchmarks are as critical as power consumption. Intel and ADI incorporated dynamic power control in their core using gated-clock circuitry. Fishman said this scheme allows the core to achieve a 10x battery life extension while operating at one-third the performance level of competitive designs.
Also lowering power demands is the combination of frequency and voltage. Frequency scaling, which can be done using clock dividers and phase-locked loops, is not new, said analyst Bier. But "with voltage scaling added, you get the benefit of the square relationship between voltage and power, thereby adding greatly to the linear power reduction achieved through frequency scaling."
But the idea of voltage scaling may have passed its prime, said Kevin Kloker, director of the StarCore architecture. "With today's IC processes and battery voltages, there's not a whole lot you can gain with voltage scaling," he argued. "This would have been really advantageous in the days of 3.3- or 5-V devices."
While the voltage range for any part using the new core depends on the implementation, ADI's Bauch argued that "at the power levels needed for portable devices, the square relationship between voltage and power makes scaling worth implementing, regardless of the process."
Bier said that in 2.5G and 3G wireless communications systems, "the power consumption of the processor is not the designer's biggest problem. There will be a lot of fixed-function or other technology required to implement wideband terminals," and the processor "may in the end not be the main power consumer in a terminal."
For multimedia, the Micro Signal Architecture incorporates instruction set enhancements that cater specifically to video, imaging, audio and voice streams. In addition, a hierarchical memory structure with a bandwidth of 2.4 Gbytes/second speeds memory accesses and overall pr ocessing.