Complete Set of Libraries Designed to Achieve Efficient Implementation and Signal IntegrityHSINCHU, Taiwan & SANTA CLARA, Calif. – May 9, 2005
-- Cadence Design Systems, Inc. (NYSE:CDN) (Nasdaq: CDN) and Faraday Technology Corporation (TAIEX: 3035) today announced that Faraday has joined the OpenChoice intellectual property (IP) program to co-develop with Cadence an extensive list of library views. The libraries are being designed to facilitate digital implementation and signal integrity (SI) under UMC's 130-nanometer Fusion process.
The library view generation process will be qualified and validated by both Faraday and Cadence research and development teams. Under the process, Faraday's customers are allowed to handle digital implementation and SI signoff in the Cadence Encounter™ digital IC design platform.
“As a long-term partner of Cadence and library provider for UMC, we are very excited with this collaboration because it allows Faraday to handle signal integrity issues for our common clients at 130 nanometers and below. We are very pleased with this extended relationship with Cadence because we were able to qualify and validate all our co-developed library views through Cadence's OpenChoice IP program,” said Jim Wang, Director of Design Development at Faraday Technology.
“To facilitate a smooth path to silicon success for our customers, Cadence is committed to open programs and standards like OpenChoice and the effective current source model (ECSM),” according to Jan Willis, senior vice president, Industry Alliances at Cadence. “We're delighted to work with Faraday to leverage our open approach and technology to provide customers with a new, SI-aware path to silicon.”
Ken Liou, director of UMC's IP Development and Design Support Division, said “Faraday's collaboration with Cadence to address SI issues at the IP level helps customers achieve faster, first-pass silicon success. We are pleased that Faraday's standard cell libraries have been validated on our 130-nanometer Fusion process.”
The co-development between Cadence and Faraday has spawned a list of library views for the UMC 130-nanometer Fusion process, high-voltage threshold (HVT) and low-voltage threshold (LVT) mixed library, including both standard logic cells and input/output (I/O) cells. The library views include qualified layout exchange format (LEF), required by chip implementation in SoC Encounter™ , which features routing by NanoRoute™ ; power grid views (PGV) for VoltageStorm® power rail analysis; and noise library (cdB) and ECSM for CeltIC™ NDC SI-aware delay calculation and crosstalk glitch analysis. Libraries for other processes will be available from Faraday soon.About OpenChoice
The Cadence OpenChoice program enables interoperability and facilitates open collaboration with IP providers to build, validate, and deliver accurate models optimized for Cadence design and verification solutions . The program aims to ensure IP quality and provide the semiconductor industry with access to optimized IP through a complete IP catalog
. This optimizes the electronics design chain and accelerates customer time to market.About Cadence
Cadence is the world's largest supplier of electronic-design technologies and engineering services. Cadence products and services are used to accelerate and manage the design of semiconductors, computer systems, networking equipment, telecommunications equipment, consumer electronics, and other electronics-based products. With approximately 4,900 employees and 2004 revenues of approximately $1.2 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose , Calif. , and trades on both the New York Stock Exchange and Nasdaq under the symbol CDN. More information is available at www.cadence.com
. Cadence, the Cadence logo, VoltageStorm are registered trademarks and Encounter, SoC Encounter, NanoRoute and CeltIC are trademarks of Cadence Design Systems, Inc. in the U.S. and other countries. All other trademarks are the property of their respective owners.