Denali's PureSpec Provides Integrated, High-quality Solution for Ethernet Designs
PALO ALTO, Calif., May 10, 2005 -- Denali today announced that its PureSpec™ verification intellectual property (IP) product now supports the verification of Ethernet designs. Denali's PureSpec product provides chip and IP designers with a comprehensive solution for modeling, simulating, and verifying Ethernet interfaces.
"PureSpec is the most trusted verification IP solution in the industry," says Vic Juneja, product marketing manager for Denali. "Denali has an excellent track record for providing high-quality verification IP for other interfaces such as PCI Express and DDR memory and we are leveraging the same proven architecture to now support Ethernet interfaces. Our customers rely on us to provide a very high-quality solution that works with all the latest testbench tools and languages for out-of-the box productivity."
"As a leading provider of communications processors and software platforms, our customers demand ultra-high reliability from our system-on-chip designs," comments Adam Malamy, verification manager at Ubicom, Inc. "Functional verification of these systems is critical, and we leverage Denali's verification IP for ensuring the correct and optimal performance of our Ethernet interfaces. Denali has delivered high quality verification IP to us, and has provided excellent post-sales customer support. This increases our productivity, and ultimately helps us to deliver successful products."
About PureSpec-Ethernet: Verification IP for Ethernet Designs
PureSpec-Ethernet is a complete verification IP solution for verifying compliance and compatibility of Ethernet designs. PureSpec verification IP includes a configurable bus functional model (BFM) that completely models the IEEE 802-3 specification, including all MAC and PHY components and all interfaces such as [S][X][R][G]MII, [R]TBI, XSBI, XAUI, and Serial.
PureSpec-Ethernet also provides a sophisticated data generation engine to help drive defined, psuedo-random bus traffic at all layers. Injected errors and error conditions are flagged and recovered according to specifications. The highly integrated nature of PureSpec-Ethernet's model behavior and data generation engine applies a sophisticated context-sensitive data generation approach to test plan execution. This enables direct translation from test plan definition to implementation, greatly accelerating the verification task and your overall verification productivity. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the design under test. PureSpec-Ethernet is architected to ensure high-quality, high-performance, and seamless integration to all EDA testbench tools and languages.
PureSpec is available now for customer evaluation at: http://www.denali.com/purespec.
Denali Software Inc. is the world's leading provider of EDA tools and Intellectual Property (IP) solutions for chip interface design, integration and verification. Its Databahn™ Design IP products offer fully configurable design cores for complex interfaces such as Serial ATA and DDR-based memory systems. Denali's PureSpec™ Verification IP product supports all complex interfaces, including PCI Express, Advanced Switching Interconnect (ASI), USB, Ethernet and Serial ATA. More than 400 companies worldwide use Denali's tools, technology, and services to design and verify complex chip interfaces for communication, consumer, and computer products. For more information, visit Denali at http://www.denali.com. Telephone: (650) 461-7200.
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