MANHASSET, N.Y. Taking solid aim at the wireless portability market, Intel Corp. and Analog Devices jointly announced today a new core architecture that incorporates digital signal processor (DSP) and microcontroller features in a single platform. The architecture is unique in its combination of both frequency and voltage scaling, which extend battery life by varying power consumption according to the demands of the application being used.
Dubbed the Micro Signal Architecture, the device incorporates a number of key features and system enhancements that will greatly extend the battery life of portable devices while speeding the processing of modem, audio, video, image and voice signals.
Ron Smith, vice president and general manager of Intel's Wireless Communications and Computing Group, pointed out today when the architecture was introduced that current DSP technology is ill-equipped to handle the extremely high data and processing rates that will be required in the move to 2.5G and 3G wireless systems. "Feedback from our customers has told us that current-generation DSPs are not satisfying their needs, and they can't be upgraded to do so," said Smith. A whole new model was required, he added.
According to Smith, the Dynamic Power Management feature allows the chip to achieve a 10x battery life extension while operating at one third the performance level of competitive designs. The system works, said Smith, by using a real-time operating system and power-management logic to monitor what's going on and modulate the frequency and voltage accordingly.
Intel and ADI announced their intent back in February to jointly develop a new architecture. "We brought together the signal-processing and real-time expertise of Analog Devices, with the data/computer processing, application and solution strength of Intel Corp., to realize a new DSP architecture that could meet the new demands," said Smith.
The result is a high-performance 16-bit co re optimized for C and C++ programmability with dynamic voltage and frequency scaling and an enhanced media instruction set.
The core comprises two multiply-accumulators (MACs), two arithmetic logic units (ALUs) and shifter functions. Each MAC is capable of performing a 16-bit by 16-bit multiply in every cycle, with an accumulation to a 40-bit result. The dual 40-bit ALUs operate on either 8-bit, 16-bit, 32-bit or 40-bit data.
While the initial version of the Micro Signal Architecture has two MACs and two ALUs, these can be scaled up or down in number, depending on the application. Now available at 300 MHz, 600 MMACs (336 MIPs), the architecture will extend to over 1 GHz, 2000 MIPs, said Smith, all while operating at about 1 V. A fully interlocked pipeline means all architecture implementations will be source-code- and binary-object-code compatible.
Microcontroller features added include byte addressing, memory protection and programmability in a higher-level language.
The microcontroller fea tures allow the single processor architecture to handle both the highly intense DSP tasks and the relatively simple control tasks. This reduces complex multiprocessor designs to a single-architecture, single-memory-map design with a single development environment, said Smith.
While performance is key, Smith emphasized the need to simplify development and speed time to market, and one way to do this is to move to higher-level languages. "Up to 80 percent of code developed for the Micro Signaling Architecture can be done in C/C++," said Smith. "This speeds time to market and widens the potential pool of developers, thereby making more code available," he said. "In addition, we also included Integrated Performance Primitives (IPPs), like those in our XScale architecture." IPPs are predefined blocks of code that reside next to the core to speed processing.
According to Will Strauss, president of research firm Forward Concepts (Tempe, Ariz.), "A unique feature in the development toolset is code profiling , whereby 'hot spots' can be identified as the program is running, allowing the developer to identify bottlenecks and thereby further optimize the code to eliminate those bottlenecks and speed up the overall performance."
For mobile applications, however, few benchmarks are as crucial as power consumption. Cognizant of this, Intel and ADI incorporated both frequency and voltage dynamic scaling that allows the system to adjust either according to the demands of the application. "The combination of both is unique," said Strauss. "No one else has done that."
Multimedia extensions to speed processing
As 3G systems gear up, with 2.5G as the stepping stone, handheld devices are in desperate need of a means to speed the processing of the incoming data such as video, imaging, audio and voice. To allow this, the architecture has incorporated enhancements to the instruction set that cater specifically to these data streams. In addition, a hierarchical memory structure with a bandwidth of 2.4 Gby tes/second speeds memory accesses and overall processing.
The hierarchy comprises a Level 1 (L1) memory closest to the core and a Level 2 (L2) memory off-chip. The latter occupies a unified 4-Gbyte space for both instructions and data. Both the L1 instruction and data memories can be configured as either static RAMs or caches, while an L1-based dedicated scratchpad data memory stores stack and local variable information.
In addition, a memory management unit (MMU) provides memory protection for individual tasks that may be operating on the core and may protect system registers from unintended access.
According to Jerry Fishman, chief executive officer of ADI, the new DSP core will be a major part of its portfolio going forward that is synergistic with the company's Othello direct-conversion GSM radio. "What we have here is DSP MIPS to burn, combined with the simplicity of programming of a microcontroller," he said.
Both companies will develop their own products based on the core, in much th e same manner as Motorola and Lucent develop their own systems based on their joint StarCore endeavor. While time frames are vague, both expect final product sometime in 2001. Third-party developers to date include CMX Systems, Hellosoft, Eonic, Hitex Development Tools, Lineo and Realogy. More information is available at the Joint Development Web site.
Silicon of the core will be released to Analog Devices and Intel development partners in early 2001.