Databahn Design Cores, PureSpec Verification IP Speed time-to-market, Reduce Risk for SATA Designs
PALO ALTO, Calif., May 18, 2005 -- Denali today announced that its Databahn™ and PureSpec™ intellectual property (IP) products now support the Serial ATA (SATA) open industry standard.
The Databahn IP for SATA is a complete, synthesizable IP core that supports SATA 1.5Gb/s and SATA 3Gb/s including Native Command Queuing (NCQ) functionality. PureSpec for SATA is a comprehensive verification IP solution that also supports optional features in the specification.
More details about Denali's Serial ATA solutions will be addressed in a two-part webcast series at: http://www.denali.com/sata_series_200505.html
- Part 1: "Serial ATA Controller IP: Delivering Bandwidth to Silicon" Presented by Brian Gardner, Denali's director of IP product marketing -- May 31, 2005, 11:00 a.m. P.D.T.
- Part 2: "Realizing the Value of Verification IP for Serial ATA Designs" Presented by Sean Smith, Denali's chief verification architect -- June 2, 2005, 11:00 a.m. P.D.T.
Serial ATA is quickly replacing parallel ATA in hard disks in desktop and mobile PCs. The SATA hard drive connector is smaller than the equivalent parallel connector, and enables data transfer rates of 1.5Gb/s and the next generation speed increase of 3Gb/s. Design teams are now using Denali's design and verification products for fast, efficient deployment of chips that support the SATA technology.
"As the industry prepares to introduce powerful 3Gb/s Serial ATA systems, PC and server builders need powerful tools to help them comply with the Serial ATA specification, as well as meet their own quality and time-to-market requirements," notes Joni Clark, SATA-IO marketing chairwoman and Seagate Technology Serial ATA marketing manager. "We welcome Denali's participation in SATA-IO and in-depth knowledge of the current SATA specification; it will prove important for Denali customers who want to enable the highest-performance Serial ATA 3Gb/s systems."
"Denali's Databahn IP products are the industry's most widely used and trusted solution for DDR memory interfaces," adds Brian Gardner. "Our SATA IP leverages the same proven infrastructure used for our DDR products. The combination of a solid and proven architecture, and the experience and support from our veteran design team makes Databahn SATA a high-quality product."
Denali's Databahn SATA core supports Serial ATA 1.0a speed and second-generation speed of 3Gb/s. It is available fully integrated with Databahn DDR memory controller or as a standalone SATA core. The direct integration with Denali's DDR memory controller core keeps SATA data off the system busses, lowering CPU overhead.
Databahn SATA also offers a simple interface to the Direct Memory Access (DMA) interface using the Intel advanced host controller interface (AHCI) specification, and a programmed I/O (PIO) mode for legacy applications and AT Attachment Packet Interface (ATAPI). Other features are configurable and programmable to offer the system architect extensive flexibility for optimal performance for a particular application.
Databahn is available now for evaluation at: http://www.denali.com/databahn.
"Verification IP is playing an increasingly critical role in chip development flows, especially for standard interfaces," remarks Sean Smith. "With more than 60 customers, our PureSpec verification IP for PCI Express is the industry standard for anyone developing a chip with that interface. Our PureSpec verification IP for SATA leverages the same proven architecture, which means customers gain a high-quality solution that works with all the latest testbench tools and languages for out-of-the-box productivity."
PureSpec for SATA is a comprehensive solution for verifying functionality, compliance, and interoperability of all Serial ATA speeds and designs at the pre-silicon stage of chip or IP core development. PureSpec verification IP includes a configurable bus functional model (BFM), protocol monitor, and complete assertion library for all SATA components in the topology, including the host and one or more SATA devices.
Composite configurations by port and function are also supported. PureSpec additionally provides a sophisticated data generation engine to help drive defined, pseudo-random bus traffic at all layers. Injected errors and error conditions are flagged and recovered according to SATA specifications. The highly integrated nature of PureSpec for SATA's model behavior and data generation engine applies a sophisticated context-sensitive data generation approach to test plan execution. This enables direct translation from test plan definition to implementation, greatly accelerating the verification task and your overall verification productivity. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the design.
PureSpec is available now for evaluation at: http://www.denali.com/purespec.
Denali Software Inc. is the world's leading provider of EDA tools and Intellectual Property (IP) solutions for chip interface design, integration and verification. Its Databahn™ Design IP products offer fully configurable design cores for complex interfaces such as Serial ATA and DDR-based memory systems. Denali's PureSpec™ Verification IP product supports all complex interfaces, including PCI Express, Advanced Switching Interconnect (ASI), USB, Ethernet and Serial ATA. More than 400 companies worldwide use Denali's tools, technology, and services to design and verify complex chip interfaces for communication, consumer, and computer products. For more information, visit Denali at http://www.denali.com. Telephone: (650) 461-7200.
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