Flexible Wafer-level Packaging Methodology Allows Same Silicon Design to Be Offered in Wire-bond or Flip-chip Bump Interconnect FormatMILPITAS, Calif., May 19 /PRNewswire-FirstCall/
-- LSI Logic Corporation (NYSE: LSI) today announced the availability of its enhanced wafer-level packaging (WLP) technology for use in ASIC/SoC designs. Packages produced in this cost-effective, high-performance technology are completely manufactured and tested at the wafer level and then mounted directly onto printed circuit boards or on discrete package substrates. WLP offers the industry's lowest cost packaging solution in an ultra small form factor with improved electrical performance. System designers making use of WLP can conserve valuable board real estate while integrating additional features into portable applications such as cell phones, PDAs and other handheld consumer devices.
The flexible WLP design methodology offered by LSI Logic enables a single design to accommodate a variety of package technology formats. By only modifying the top metal layer, the chip design can be re-configured for flip-chip, wire-bond or direct chip attach interconnect solutions. With this approach, system designers gain considerable design flexibility and intellectual property (IP) re-use with minimal development effort, thereby drastically reducing non-recurring engineering (NRE) costs and speeding time-to-market.
"WLP technology broadens the LSI Logic packaging portfolio and enables more flexible system-level design solutions where a small form factor is required," said Stan Mihelcic, director of Packaging and I/O Marketing at LSI Logic. "Our unique methodology also provides our customers with the additional flexibility of accommodating either a wire-bond or flip-chip bump interconnect format. This is especially important for system designers who require variations of a standard chip design utilizing deep-submicron ASIC/SoC technology."
The die in a WLP format can be connected directly to the host system board, eliminating traditional packaging parasitics. This electrical performance enhancement enables more flexible system-level design solutions for high performance memory interfaces and serializer/deserializer (SerDes) technology where stringent system timing budgets continue to challenge system designers.
By leveraging existing wafer processing techniques, engineers can co-design and develop an optimal bump layout to suit the particular application. A typical concern with die only packages has been the ability to provide a fully tested "Known Good Die" (KGD) product. However, with advanced wafer level test methodologies and wafer level reliability offered by LSI Logic, true KGD products are possible requiring no additional package level final test.
In addition to portable handheld consumer devices, WLP technology also enables new product growth in industrial, medical and military applications that require a small form factor. LSI Logic supplies ASIC/SoC solutions to these markets with domestic manufacturing capability. Customers adopting WLP can make use of standard surface mount assembly techniques without changing existing equipment and processes. WLP offered by LSI Logic is available in both eutectic and RoHS compliant lead-free solder terminations, eliminating the use of hazardous leaded solder material from the manufacturing process.Availability
WLP solutions are available today in high volumes to LSI Logic customers.About LSI Logic Corporation
LSI Logic Corporation focuses on the design and production of high-performance semiconductors for Consumer, Communications and Storage applications that access, interconnect and store data, voice and video. LSI Logic engineers incorporate reusable, industry-standard intellectual property building blocks that serve as the heart of leading-edge systems. LSI Logic serves its global OEM, channel and distribution customers with standard-cell ASICs, Platform ASICs and standard products, host bus adapters, RAID controllers and software. In addition, the company supplies storage network solutions for the enterprise. LSI Logic is headquartered at 1621 Barber Lane, Milpitas, CA 95035. http://www.lsilogic.com
.SOURCE LSI Logic Corporation"Safe Harbor" Statement under the Private Securities Litigation Reform Act of 1995: Statements in this press release regarding LSI Logic's business which are not historical facts are "forward-looking statements" that involve risks and uncertainties. For a discussion of such risks and uncertainties, which could cause actual results to differ from those contained in the forward-looking statements, see "Risk Factors" in the Company's Annual Report or Form 10-K for the most recently ended fiscal year.