Xilinx Strengthens DSP IP Library with New Floating-Point and Digital Video Broadcasting S2 Cores

SAN JOSE, Calif., May 19, 2005 - Xilinx, Inc. (NASDAQ: XLNX) today announced the immediate availability of its latest Digital Signal Processing (DSP) IP library based on Xilinx Virtex™-4 FPGAs and Spartan™-3E FPGAs. Updates to the library include a suite of Floating-Point Operators, a DVB FEC encoder core, and key enhancements to existing cores including Turbo Convolutional Decoder UMTS/3GPP, Reed Solomon Decoder, Reed Solomon Encoder, Viterbi Decoder, Direct Digital Synthesizer, MAC FIR filter, Complex Multiplier core and Multiplier Accumulator. Enhancements to these cores include full support for the latest ISE 7.1i development tool and greater optimization for performance, silicon utilization or both. Designers can immediately download the new DSP library and other IP cores in the latest release at www.xilinx.com/ipcenter.

The new Floating-Point LogiCORE™ module developed in conjunction with Qinetiq, delivers tens of Giga Floating-Point Operations per Second (GFLOPS) and supports processing requirements in advanced communication and radar systems. The new core, included with Xilinx ISE™ software, enables customers to reduce component count, thus reducing overall system cost by performing the Floating-Point arithmetic using the FPGA.

The new Digital Video Broadcasting Satellite Version 2 (DVB-S2) FEC Encoder core for performing FEC in DVB-S2 system is based on concatenation of Bose-Chaudhuri-Hochquenghen (BCH) with Low Density Parity Check (LDPC). The inner coding brings the performance at times only 0.7dB from the Shannon limit, providing an extremely high encoding output rate of about 700Mbits/s using Xilinx Virtex-4 devices.

"The release of the new floating-point operator library supports customers developing advanced communication systems in the broadband, 4G, beyond 3G (B3G) and JTRS space. These operators are key functions required for delivering numerically robust implementations of QR-decompositions (QRD) matrix inversion, singular value decomposition and Cholesky factorization for beam forming and MIMO processing," said Dr. Chris Dick, chief DSP Scientist at Xilinx. "Parallel configurations of the new operators in our Virtex-4 device technology delivers the high-performance required in advanced wireless systems in a cost effective manner."

About the Floating-Point Operator Core
The Floating-Point Operator core delivers exceptionally high Floating-Point arithmetic performance through parallelism, enabling a finer weight calculation in advance adaptive signal processing system, e.g. Smart Antenna System. The arithmetic word length in this system can be reduced below IEEE754 single precision, allowing substantial savings in FPGA resources and power consumption.
Key features include:

• IEEE-754 standard compliant floating-point operators, supporting add/subtract, multiply, divide, compare and square-root operations
• Can be configured for high-speed operation with an instruction issued on every clock cycle
• Parameterized fraction and exponent word lengths, including single and double precision
• Includes multi-cycle divide to reduce resource requirements for single precision

About the DVB-S2 FEC Encoder Core
The DVB-S2 FEC Encoder core provides designers with an FEC encoding block for DVB-S2 systems. To increase the throughput of the core, the input and output data word length can be widened to allow internal parallel processing of the data.
Key features include:

• Forward Error Correction for DVB-S2 supporting all code rates and both normal as well as short frames
• Allow parallelization to increase throughput by setting the number of input/output bits to 4
• Fully optimized for speed and area
• Fully synchronous design using a single clock
  

Pricing and Availability
All cores are available now from Xilinx at: www.xilinx.com/dsp. The Floating-Point Operator is included with the latest version of the Xilinx CORE Generator™ System. For a limited time, customers can use the Floating-Point Operator IP at no cost (standard list price of $995). The DVB-S2 FEC Encoder core is available as separately licensed parameterized netlists. The license price for the DVB-S2 FEC Encoder core is USD $1000.

About Xilinx
Xilinx is the worldwide leader in complete programmable logic solutions. For more information, visit www.xilinx.com.

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