Toshiba, others gain silicon advantage from production use of CellMath tools
MENLO PARK, Calif. - May 30, 2005 - Arithmatica, Inc., the first company focused solely on using advances in silicon math algorithms to lower costs and power, and increase speed for math-intensive ICs, today expanded its product scope to include EDA tools. The company announced availability of its CellMathT tools line with two proven standard cell-based design tools that can improve silicon efficiency by as much as 40 percent without requiring any change in design practices. These new tools, which deliver Arithmatica's silicon math know-how to datapath-intensive modules, include:
- CellMath Designer - Provides a unique datapath design environment including support for integer, fixed-point and carry-save arithmetic, configurable floating-point functions, timing engine, auto-pipelining, logic optimization based on multiple proprietary microarchitectures, and operator merging and logic sharing across the entire datapath;
- CellMath Builder - Configures a library of silicon-efficient, floating-point functions based on user performance goals and options such as bit width, internal accuracy and pipeline stages.
The CellMath tools line complements Cadence, Magma, and Synopsys synthesis, physical synthesis, and verification flows. CellMath tools generate bit- and cycle-accurate C and Verilog models for simulation and formal verification, and technology-specific netlists for integration into chip-level netlists during physical synthesis. The models and netlists produced provide an efficient means to formally verify the netlist to the behavioral model, relieving the significant verification bottleneck typical in complex datapath design.
Demonstrated impact in power, performance, area
Designers have used CellMath tools for 130, 90 and 65nm process nodes, and results have been validated with functional silicon and volume shipments. Tool use among Arithmatica's first five tools licensees spans a broad range of applications, from 3D graphics and multimedia to embedded computing and communications. These users report typical datapath power, performance and/or area (PPA) improvements in the range of 20-40 percent with the same or improved timing. After careful evaluation, Toshiba and Digital Media Professionals (DMP) chose CellMath tools for designs targeted for production applications.
"Toshiba has licensed CellMath Designer to design ICs for consumer electronics applications with our 65nm process technology," Mitsuo Saito, Chief Fellow, Semiconductor Company, Toshiba Corporation, stated. "After extensive evaluation of real designs, it was clear that CellMath Designer helped us achieve our aggressive performance goals and reduce die area. Our datapath results show an average 20% area savings. Learning CellMath Designer was easy; our design team was able to use the tool and achieve good results after two afternoons of training."
"We licensed CellMath Builder to gain access to floating point functions that significantly improve the performance and the area of our graphics processor products," said Tatsuo Yamamoto, CEO, Digital Media Professionals Inc. "CellMath Builder's automation and built-in timing engine give us the ability to explore many different architectures early in the design process, something that would never be easy, given our schedule, when hand coding these functions. This gives us higher quality and higher performance designs and allowed us to focus on differentiating our product in core graphics features."
Dave Burow, Chairman of Arithmatica, said, "Datapath design is a critical and growing area in a host of applications required for the consumer electronics market, including 3D graphics, imaging, multimedia, embedded processing, and communications. We are pleased that technology leaders Toshiba, DMP and others are successfully deploying our new CellMath tools to improve the speed, area and power consumption of their next-generation products."
Pricing and Availability
Arithmatica actively markets and supports its products in North America, Europe, Japan, Korea and Taiwan. CellMath Designer and CellMath Builder are production-released and available under an annual term license. Annual campus licenses fees in North America are US$129,000 for CellMath Designer and US$89,000 for CellMath Builder. Arithmatica also offers multi-year term and global WAN licensing options.
Arithmatica is the first company focused solely on using advances in silicon math algorithms to lower costs and power and increase speed for math-intensive ICs, such as those used in 3D graphics, imaging, multimedia, wireline and wireless communications, and embedded processing. Its unique technology, available through its tools products and design services, provides differentiated improvement to licensees' ICs. The company received its first venture funding in 2001 and is headquartered in Menlo Park, Calif., with a research and development center in Warwick, UK. For further information about how its silicon math solutions increase silicon efficiency and boost productivity, please visit: www.arithmatica.com.
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Note to Editors: Arithmatica, the Arithmatica logo and CellMath are trademarks of Arithmatica, Inc. All other trademarks and registered trademarks belong to their respective companies.