TSMC Taps Virage Logic for 65nm Memory Compilers
FREMONT, Calif., May 31 /PRNewswire-FirstCall/ -- TSMC (NYSE: TSM; TSE: 2330), the world's largest semiconductor foundry, has tapped Virage Logic Corporation (Nasdaq: VIRL), a pioneer in Silicon Aware IP(TM) and leading provider of semiconductor intellectual property (IP) platforms, to develop libraries in support of early users of TSMC's 65 nanometer (nm) Nexsys(SM) process technology. The agreement provides integrated circuit (IC) designers with much-needed memory compilers for leading-edge system-on-chip (SoC) design.
"At every new technology node, the amount of chip space taken by on-chip memory increases dramatically," said Edward Wan, senior director of design service marketing for TSMC. "At the 65nm node, on-chip memory may occupy more space than logic or any other IP and therefore it's important for our customers to get early access to advanced memory compilers."
Virage Logic is both a long-time provider of library products for a range of TSMC processes and a distributor of TSMC-developed libraries. Virage Logic is currently working with TSMC in developing 65nm memory compilers and will offer multiple memory architectures for TSMC's 65nm processes to meet specific needs in high-density, high-speed and ultra-low power applications.
"Our collaboration with TSMC on the 65nm memories underscores Virage Logic's continuing technology leadership at the advanced process technologies of 130nm and below," said Jim Ensell, vice president of marketing and business development for Virage Logic. "This agreement with TSMC is the first of our 65nm announcements and provides further validation of Virage Logic's Silicon Aware IP initiative. Introduced earlier this year, this initiative calls for the tight integration of physical IP, such as memories, logic and I/Os, with infrastructure IP for test, diagnostics, repair and yield enhancements. This combination results in high-yielding, highly reliable semiconductor IP at 130-, 90- and now 65nm. By significantly increasing yields, sometimes as much as 250 percent, Virage Logic's Silicon Aware IP removes the barrier to advanced process entry."
About Silicon Aware IP
Silicon Aware IP is Physical IP, such as memories, logic and I/Os, designed with embedded Infrastructure IP for test, diagnostics, repair, and yield enhancements. The result is IP that is high yielding and enables rapid time-to-volume at advanced process nodes such as 130nm, 90n, and now 65nm. In addition, Silicon Aware IP results in much higher test quality and reliability. Today, Virage Logic believes it is the only IP provider to offer Silicon Aware IP, an example of which is its Self-Test and Repair (STAR) Memory System(TM). The company's Silicon Aware IP initiative calls for its entire product portfolio to become Silicon Aware IP over time.
Virage Logic will develop a variety of its STAR and Area, Speed and Power (ASAP) Memory(TM) products to support multiple TSMC process variants and architectures. The first Virage Logic views of the new IP will be available to designers in the third quarter of the year. First Virage Logic commercial products will be available in the fourth quarter on TSMC's 65nm low-power (LP) and generic (G) processes. Virage Logic will also develop compilers for the TSMC 65nm high-speed (HS) process that will be available in 2006.
About Virage Logic Corporation
Founded in 1996, Virage Logic Corporation rapidly established itself as a technology and market leader in providing advanced embedded memory intellectual property (IP) for the design of complex integrated circuits. Today the company is a global leader in semiconductor IP platforms comprising embedded memories, standard cells, and I/Os and is pioneering the development of a new class of IP called Silicon Aware IP. Silicon Aware IP tightly integrates Physical IP (memory, logic and I/Os) with the embedded test, diagnostic, and repair capabilities of Infrastructure IP to help ensure manufacturability and optimized yield at the advanced process nodes. Virage Logic's highly differentiated product portfolio provides higher performance, lower power, higher density and optimal yield to foundries, integrated device manufacturers (IDMs) and fabless customers who develop products for the consumer, communications and networking, hand-held and portable, and computer and graphics markets. The company's comprehensive quality efforts are validated in its FirstPass-Silicon Characterization Lab, which helps ensure high quality, reliable IP across a wide range of foundries and process technologies. Headquartered in Fremont, California, Virage Logic has R&D, sales and support offices worldwide. For more information, visit www.viragelogic.com.
SAFE HARBOR STATEMENT FOR VIRAGE LOGIC UNDER THE PRIVATE SECURITIES LITIGATION REFORM ACT OF 1995:
Statements made in this news release, other than statements of historical fact, are forward-looking statements, including, for example, statements relating to trends, business outlook, products, and customer relationships. Forward-looking statements are subject to a number of known and unknown risks and uncertainties, which might cause actual results to differ materially from those expressed or implied by such statements. These risks and uncertainties include Virage Logic's ability to forecast its business, including its revenue, income and order flow outlook; Virage Logic's ability to execute on its strategy to become a provider of semiconductor IP platforms; Virage Logic's ability to continue to develop new products and maintain and develop new relationships with third-party foundries and integrated device manufacturers; adoption of Virage Logic's technologies by semiconductor companies and increases or fluctuations in the demand for their products; the company's ability to overcome the challenges associated with establishing licensing relationships with semiconductor companies; the company's ability to obtain royalty revenues from customers in addition to license fees, to receive accurate information necessary for calculating royalty revenues and to collect royalty revenues from customers; business and economic conditions generally and in the semiconductor industry in particular; competition in the market for semiconductor IP platforms; and other risks including those described in the company's Annual Report on Form 10-K for the period ended September 30, 2004, and in Virage Logic's other periodic reports filed with the SEC, all of which are available from Virage Logic's website (www.viragelogic.com) or from the SEC's website (www.sec.gov), and in news releases and other communications. Virage Logic disclaims any intention or duty to update any forward-looking statements made in this news release.
SOURCE Virage Logic Corporation