Fremont, California, June 3, 2005 — Genesys Testware, Inc., a leading supplier of yield, quality and cost optimization tools for nanometer ICs, announced today the addition of efficient automated insertion of embedded test and repair circuits for memory into system IC designs to it’s ArraytestMakerTM product. The Genesys solution enables IC designers to automatically insert embedded test and repair circuits during the logic synthesis phase of design implementation. Competing solutions insert embedded test circuits before logic synthesis at register transfer level or after logic synthesis at gate level. In addition to this new implementation step, a validation (equivalence checking or simulation) step is needed to verify that the original functionality is preserved. The new Genesys solution eliminates these two steps in the design implementation process, reducing both cost and turn-around time.
IC designers using ArraytestMakerTM can now specify the hierarchical path name of each memory instance in the design using Tcl variables. In turn, ArraytestMakerTM generates a synthesis script to insert memory test, diagnosis and repair circuits into the user design. The insertion synthesis script utilizes common synthesis commands to add instances, ports and wires to sub-designs. This synthesis script can then be included in the top-down synthesis script for the user design itself. Automated insertion using popular logic synthesis tools like Synopsys Design Compiler and Cadence RTL Compiler is currently supported. Support of Magma Blast-Create is planned for the fourth quarter of 2005. Automated insertion of embedded test and repair circuits for memory at gate level after logic synthesis is also supported in a similar way.
“We are pleased to learn about the addition of efficient automated insertion of embedded test and repair circuits for memory to Genesys ArraytestMaker†said Mo Tamjidi, President of Dolphin Technology Inc., a leading provider of high performance embedded memory and memory compiler products. “I am sure that all of our mutual customers will find this new feature very usefulâ€.
“Nanometer IC contain hundreds of memory instancesâ€, said Bejoy Oomman, President of Genesys Testware. “Automated insertion of embedded test and repair circuits to nanometer memories reduces designer effort while eliminating costly errors.â€
The new solution also supports the sharing of an embedded test and repair circuit between several memories at different levels of hierarchy to reduce area overhead. The Genesys automatic insertion solution also supports hierarchical designs and maintains the original design hierarchy to simplify engineering changes and debug. Synthesis exception constraints for each embedded test and repair circuit for memory are also aggregated into constraints for the entire design.
Automated insertion of embedded test and repair circuits for memory will be available at no additional cost to existing users of ArraytestMakerTM during the third quarter of 2005.
This new feature will be demonstrated during the upcoming 42nd Design Automation Conference that will be held from June 13-17, 2005 at the Anaheim Convention Center, Anaheim, California in Exhibitor Booth #1080.
About Genesys Testware Genesys Testware, Inc. provides tools to improve yield, quality and cost of nanometer ICs. Its products are all silicon-proven in various customer designs. Genesys Testware’s corporate headquarters are located at 76 Whitney Place, Fremont, CA 94539. For more information, please visit the company’s web site at
http://www.genesystest.com ArraytestMaker is a trademark of Genesys Testware, Inc. All other trademarks or registered trademarks are the property of their respective owners.
