WAKEFIELD, MA--Jun 6, 2005
-- The VSI Alliance (VSIA) today announced the release of the VSIA QIP Metric 2.0, developed by VSIA and FSA member companies. These world-leading semiconductor, Electronic Design Automation (EDA) and Semiconductor Intellectual Property (SIP) providers developed the metric to address the need to measure quality of SIP cores in order to ease integration efforts. This is a benefit to both the providers and integrators of SIP. After completing beta evaluation, the Metric will be available to anyone at no charge.
The VSIA QIP Metric is a tool that can aggressively reduce the time typically required to make an IP purchase decision and to integrate the core. The Metric helps the IP vendor and IP consumer communicate based on an objective foundation. Besides setting up the basis for measuring a core's characteristics against an industry-approved list of attributes, the standard provides a view of the IP vendor's general approach to IP development. This, in turn, levels the playing field for vendors and allows an integrator to evaluate similar cores from competing vendors.
"Accurately assessing IP providers in order to determine IP quality continues to be one of the greatest challenges facing the SoC industry today," said Mike Kaskowitz, GM of Mentor Graphics' IP Division and VSIA's president. "As the leader in creating industry standards for IP and SoCs, VSIA's new QIP Metric provides the basis for measuring a core's characteristics against an industry-approved list of attributes. As a leading IP supplier, Mentor believes that the metric will shorten the IP sales cycle and allow the Company to showcase their IP cores through an objective scoring system."
Several leading semiconductor intellectual-property (IP) vendors and users that are members of the VSIA or of the FSA will participate in a beta program that will begin on June 20, 2005. These companies include Agilent, Cadence Design Systems, Cirrus Logic, Conexant, Freescale Semiconductor, LSI Logic, Matrix Semiconductor, Mentor Graphics, NVIDIA, Philips and STMicroelectronics. In addition, a limited number of FSA and VSIA members can apply to become QIP 2.0 beta test companies. Those interested members are invited to apply for the beta program online at http://www.vsi.org/QIPBeta/. In approximately six months, when the beta phase of the program is complete and input is incorporated, the Metric will be available to any company at no charge.
IP Quality Pillar Member Companies
Kathy Werner, Freescale IP Reuse Manager, serves as chairperson over the VSIA and FSA groups working on the development of the Metric. These companies include: Cadence Design Systems, Freescale Semiconductor, LSI Logic, Mentor Graphics, Philips, STMicroelectronics and TSMC.
New in QIP 2.0
Since its initial release in August 2003, the VSIA QIP Metric has undergone rigorous beta trials, and version 2.0 reflects the feedback from this beta testing. The new version of the metric is easier to use than its predecessor and is more streamlined. New in 2.0 is a vendor qualification worksheet, applying to all IP from a vendor, covering development processes, quality assurance, design and support infrastructure, and other general corporate capabilities. This version also has simpler IP-qualification metrics covering documentation, deliverables, and information specific to the IP integrator as well as IP development practices. The VSIA QIP Metric 2.0 includes the newly added vendor assessment and the requirements for Soft IP have been restructured and revisited. Legacy worksheets, taken from the previous QIP Metric version, include software IP, verification IP and hard IP worksheets, including digital and analog/mixed signals -- these will be updated in future QIP Metric releases.
QIP Metric Endorsement
Cadence Design Systems, Freescale Semiconductor, LSI Logic, Philips and STMicroelectronics will participate in the beta testing of 2.0 and, going forward, will require that IP vendors provide scores when delivering new IP cores. Mentor Graphics and Chipidea, IP vendors, have been providing scores to their customers based on the Alpha version of QIP Metric.
"As a leading SoC provider of high-speed interconnect products in the storage, communications and consumer markets, providing high-quality IP to our customers is imperative," said Jean Bou-Farhat, vice president CoreWare® Technology, LSI Logic Corporation. "For more than a decade, our CoreWare IP methodology drove our SoC success. Today, we continue that success with the adoption of VSIA's QIP 2.0 metric, which will accelerate the use of IP from third-party suppliers for SoC designs."
View additional endorsements from Cadence Design Systems, Chipidea, FSA, LSI Logic, Mentor Graphics, Philips Semiconductors, and STMicroelectronics at http://www.vsi.org/news/pressrelease/QIP_Metric_Quotes.pdf
QIP Metric Pricing and Availability
Following DAC in June 2005, the VSIA QIP Metric 2.0 will be released for a beta test period to selected VSIA and FSA members. Following the beta test period, QIP Metric 2.0 will be released to the general public at no charge.
The VSI Alliance (VSIA) is an open, international organization that includes representatives from all segments of the SoC industry: System houses, Semiconductor vendors, Electronic Design Automation (EDA) companies, and Intellectual Property (IP) providers. VSIA's mission is to dramatically enhance the productivity of the SoC design community by providing leading edge commercial and technical solutions and insight into the development, integration and reuse of IP. VSIA has wide industry participation with more than 70 member companies from around the world. Membership is open to any company with an interest in the development and promotion of business solutions and open standards used in the design of System-on-Chip. For more information, visit the VSIA web site at www.vsi.org, or e-mail to email@example.com.
The VSI Alliance is a trademark of the Virtual Socket Interface Alliance. All other brands or trademarks are the property of their respective holders and should be treated as such.