Temento Systems announces PSL On Chip Verification (OCV) in new DiaLite Edition & the Release 4.5

Montbonnot, France, June 2nd, 2005 – Temento Systems is announcing at DAC 2005, the 4.5 commercial release of DiaLiteTM, its innovative debug and verification tool.

The new Platform Edition completes the DiaLiteTM products range from FPGA to SoC :

A PSL Assertion Checker module is now available to enable At Speed properties verification, directly on the chip including PSL 1.1 language support, PSL IP automatic generation and insertion and PSL debug manager. This Edition takes advantage of the DiaLiteTM Instrumentation benefits and complex PSL functions can be associated with triggers IP cores. Combining the instrumentation IP cores on a same platform enlarge the debug possibilities like never done before.

PSL On Chip Verification (OCV) will allow designers to create PSL properties (A Boolean & temporal set of expressions describing system behaviour) that address their design checking requirements. Working with assertions provides more information and can drastically improve the understanding of the internal behavior of the design. Implementing DiaLiteTM PSL Assertion Checker as part of the design process will create in any case a considerably higher quality of design and speed up time-to-market.

R4.5 main new features and enhancements :

The support of the Xilinx native TAP (Spartan 3, II, IIE and Virtex E, II, II Pro) that will improve efficiency and performance of all instrumentation projects using it. This Feature will soon be followed during the year by the support of Altera native TAP
The support of project Import/Export for Synplify Pro®, LiberoTM, ISE along in addition to Quartus® II and Design Compiler® FPGA
A step by step debug mode that allows to read Instruments results even when the System Clock is stopped, also completed with a full independence of System and JTAG clocks
A more efficient HDL Fault Finder, already known as the only tool leading to a true productive debug using the waveforms to direct you to the part of code in default

About Temento Systems

Temento Systems S.A. provides Electronic Design and Test Automation (EDTA) solutions, that enable to test, and to debug electronic products (System on Chip (SoC), FPGAs, Boards, Multi-Chips Modules (MCMs), and Systems). Unlike traditional EDA software providers, Temento Systems offers a broad range of solutions focused on systems design test, starting from the earliest stage of design definition (virtual test), straight through hardware testing (physical test). Temento's solutions are used by product development teams, manufacturing teams, maintenance teams, in major companies, and SME in the semi-conductor, telecommunications, consumer electronics, computer, automotive, and aerospace industries. For more information, visit the Temento web site at http://www.temento.com.