PALO ALTO, Calif., June 9, 2005 -- Denali today announced that Atheros Communications, Inc., a leading developer of advanced wireless LAN (WLAN) chipsets, has selected Denali's PureSpec™ verification intellectual property (IP) products for its chip design and verification efforts.
Atheros engineers are using PureSpec™ at the pre-silicon stage of verification to model and simulate interactions with other devices across USB, PCI Express and Ethernet interfaces in the chip design. PureSpec enables Atheros to ensure correct and optimal design of its chip interfaces, ultimately increasing verification productivity and overall product quality.
"PureSpec is the most widely used verification solution for PCI Express designs," notes David Lin, Denali's vice president of Product Marketing. "We are seeing this same level of customer acceptance in our PureSpec products for Ethernet and USB. Atheros has implemented a leading-edge design and verification environment that enables them to bring to market high-quality products quickly. We are pleased to have them as a customer, and we are committed to their continued success."
"Functional verification of our chip designs plays a crucial role in supporting our rapid time to market for new products, such as the industry's first and only single-chip PCI Express solution for wireless LAN," says Rick Bahr, vice president of engineering for Atheros. "Denali has a product well architected to support our directed and random testing. We are now leveraging that same product architecture to address the functional verification of our USB and Ethernet interfaces, just as we did initially with PCI Express."
PureSpec is a comprehensive solution for verifying functionality, compliance and interoperability of design interfaces at the pre-silicon stage of chip or IP core development. PureSpec verification IP includes a configurable bus functional model (BFM), protocol monitor, and complete assertion library for all components in the topology, including the host and one or multiple devices. Composite configurations by port and function are also supported. PureSpec additionally provides a sophisticated data generation engine to help drive defined, pseudo-random bus traffic at all layers. Injected errors and error conditions are flagged and recovered according to specifications.
The highly integrated nature of PureSpec model behavior and data generation engine enables a sophisticated context-sensitive data generation approach to test plan execution. This enables direct translation from test plan definition to implementation, accelerating the verification task and productivity. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the design.
PureSpec supports a number of standard interfaces, including: PCI Express, Advanced Switching Interconnect (ASI), USB, Ethernet and Serial ATA.
PureSpec is available now for customer evaluation at: http://www.denali.com/purespec.
Denali Software Inc. is the world's leading provider of EDA tools and Intellectual Property (IP) solutions for chip interface design, integration and verification. Its Databahn™ Design IP products offer fully configurable design cores for complex interfaces such as Serial ATA and DDR-based memory systems. Denali's PureSpec™ Verification IP product supports all complex interfaces, including PCI Express, Advanced Switching Interconnect (ASI), USB, Ethernet and Serial ATA. More than 400 companies worldwide use Denali's tools, technology, and services to design and verify complex chip interfaces for communication, consumer, and computer products. For more information, visit Denali at http://www.denali.com. Telephone: (650) 461-7200. Email: firstname.lastname@example.org.
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