FPGA users taxed but satisfied

Despite areas of commonality, the survey accentuated ways in which FPGA design is different from IC/ASIC design. Some things are obvious: FPGAs cost less to design and take less time, but gate counts and clock speeds are lower. There are other differences, however. For one, FPGA designers appear to be much more versatile when it comes to tackling a range of design tasks.

The median FPGA gate count is 920,000 today, going up to 2 million in two years, compared with an expected

4.2 million by IC designers. The median clock speed today is 128 MHz, compared with 349 MHz for IC design. But one data point is fairly close: A full 21 percent of the equivalent-logic gates on an FPGA are taken up by intellectual-property blocks that are designed by others.

FPGAs indeed are becoming complex systems-on-chip. Currently, 56 percent of designers said they incorporated DSP blocks, 40 percent incorporated microprocessor cores and 33 percent added serializer/deserializer blocks to their FPGA designs. Most of those functions are implemented in FPGA logic cells, although there's some use of embedded hard macros.

FPGAs aren't necessarily quick and easy knockoffs. The mean time to market for an FPGA design is nine months, compared with 14 months for ICs; and the mean cost is $1.9 million, compared with $8.8 million. The median FPGA design cost is $400,000, compared with $2.1 million for IC design.

Many hats
While no more than 25 percent of IC designers do any one task, an FPGA designer is much more of a jack-of-all-trades. Sixty-three percent do register-transfer level design, 55 percent do RTL verification, 62 percent do synthesis and 66 percent do placement and routing themselves. Some 24 percent do embedded-software development, compared with just 3 percent of IC designers. And 46 percent do architectural definition — nearly twice the rate of IC designers.

The most critical challenges for FPGA designers are meeting timing budgets (71 percent), getting the FPGA to work on the pc board (66 percent) and completing functional verification (56 percent). Signal integrity and power come next. FPGA designers seem least concerned about intellectual-property selection and verification, minimizing die size and using all available gates. In this area, 60 percent say they're taking full advantage of device gate capability.

The era of gate-level schematic design is clearly over. Of those responding, 95 percent say they use synthesis, 85 percent use HDL simulation and 69 percent use FPGA floor planning or prototyping. Twenty percent use SystemVerilog today, with 36 percent of the designers expecting to use it in two years.

As in ICs, electronic system-level design seems to be catching on. Some 19 percent use C-language modeling today, with 38 percent expecting to use it in two years. C-language synthesis is at 14 percent today, moving to 30 percent in two years, while SystemC is used by 13 percent today, with 34 percent expecting to adopt it in two years.

Also, as with IC designers, FPGA designers are most satisfied with the accuracy of their EDA tools. But the level of satisfaction is higher among FPGA designers, who checked in at 50 percent, compared with 40 percent for the IC designers. In fact, FPGA designers indicated higher levels of satisfaction in response to almost every question. The area of least satisfaction is multivendor interoperability (24 percent).

When asked which types of tools they are most satisfied with, FPGA designers point to tools for simulation, routing and extraction/analysis. They are least satisfied with those for formal verification, and for power and signal integrity analysis. In terms of overall experience with EDA vendors, 90 percent said they were very or somewhat positive about technology, compared with 78 percent for the IC designers.

The 10 most frequently used FPGA tool providers are, in order, Xilinx, Altera, Synplicity, Mentor Graphics, Synopsys, Actel, Cadence, Lattice Semiconductor, Aldec and QuickLogic. The highest satisfaction rating was with Synplicity, at 73 percent.

When it comes to licensing, there seems to be a disconnect with EDA vendors. While 57 percent of FPGA designers use time-based licenses of three years or less, 61 percent would prefer perpetual licenses; only 17 percent prefer the three-year TBLs.

Many of the verbatim comments have to do with software quality and ease of use. "Pay more attention to software bugs," one designer wrote. "Improve quality and interoperability of tools," said another. "Improve error messages so they are less cryptic," said a third.

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