When I looked into possible ways to solve some of the problems that block the trade of analog intellectual property recently, some interesting ideas emerged. In principle, there should be a big demand among ASIC and system-on-chip designers for analog IP: amplifiers, data converters and interface components. But these devices behave differently on SoCs than they do on the digital blocks.
Even with massive documentation, it's nearly impossible to codify all the IC design and layout procedures required to get these devices to work properly. Thus, analog IP property trade has historically seemed more of a design services business, in which an engineering team is required to recommend layout and test procedures for every piece of IP that goes out the door.
It turns out that digital designers have many of the same issues. Simulation models and documentation for IP are barely up to the task; process models are sketchy on yield information and seldom keep up with updates and tweaks (even from a supermarket like TSMC). During a panel at this spring's International Symposium on Quality in Electronic Design (ISQED), even audience members complained. They said they feel cheated when the IP they get is poorly supported, and doesn't work as advertised. "Why can't somebody police this stuff?" they asked. (See "ISQED panel takes on IP roadblocks" at www.eetimes.com and search for article ID: 159904078; and "IP quality: design's tough nut," also at eetimes.com, article ID: 160901312.
Some of this is reminiscent of the incoming inspection issues I used to face as a marketing manager for fully packaged parts. A customer would complain, "Your parts don't meet spec," and I'd have to ask, "How are you testing them?" (The means of verifying a specification for a standalone part were often more controversial than the spec itself. It's undoubtedly worse for an IP, which must perform in conjunction with some other blocks for which it has never been tested.)
It occurred to me during the ISQED panel that there might be a good business opportunity for a third-party IP characterization service.
Though they are not offering any form of IP characterization, Ken Kundert and Henry Chang of Designer's Guide Consulting (Los Altos, Calif.) were enthusiastic about the possibilities for analog IP trade-and offered useful advice on how to make it work. Kundert, an expert in simulation, is credited with developing the Spectre RF time-domain simulator for Cadence Design Systems (and, earlier, with development of the harmonic balance simulator for EEsof when that company was under the Hewlett-Packard umbrella). Chang, another Cadence alumnus, had chaired the VSI Alliance on analog property trade. They visited with me in San Francisco recently.
"For ASIC designers, analog always has been and always will be an interface technology," said Chang, putting things in perspective. "Phase-locked loop and serdes [serializer/deserializer] designers are analog designers," he said.
"No matter what you do, you need to be able to drive signals off-chip. At the edge of the box, the edge of chip, data rates are 1 Gbit/second, 2.5 Gbits, 5 and 6.25. It's going to be 10 Gbits/s very soon," Chang explained. "At those speeds, you're looking at an ugly signal with a lot of modulation."
Kundert was concerned with the verification plans ASIC designers were implementing. A top-down verification plan would ensure model consistency between high-level language models and transistor-level models, he said. But such a plan should also incorporate third-party IP.
"Digital design has a well-documented verification process," Kundert said. "There is typically no such thing for analog. Designers do their own verification."
In other words, designers traditionally develop their own verification plans. But how do you develop verification process from a data sheet that itself is subject to errors? The analog intellectual-property provider could provide the verification tools with the IP, Kundert suggested. An example would be a noise generator for the simulator.
Even for a guy used to trading standalone semiconductors, Kundert's suggestion was something of a revelation: Instead of having to ask, "How are you testing these?" in response to the call that says, "Your parts don't work," you provide the instructions for testing it up front with the part (or IP) itself. It could solve a lot of problems.
Verification IP-test instructions, tools and suites for specific properties-has become part of the "services" offered by IP vendors like Denali Software Inc. (Palo Alto, Calif.) and Knowlent Corp. (a startup in Santa Clara, Calif.). Denali provides memory interface IP while Knowlent specializes in off-chip interfaces like PCI Express, Serial ATA, USB 2.0, Gigabit Ethernet, Xaui, Infiniband and RapidIO. As with any analog component, the interface-IP blocks are capable of manipulating signals with complex modulating and timing requirements. The verification IP includes plans and tools for verifying that those interfaces-instantiated in a new SoC-perform according to their specifications.
Denali's business, which began as verification of memory models, turned into the design of double-data-rate controllers and, most recently, a universal memory controller, said marketing vice president Kevin Silver. Delivery of IP depends on an IP infrastructure-one that includes verification, he said. "Customers do not want their IP vendors to be a design service. IP consumers resent testing incoming IP; but verification is 80 percent of the [design-in] problem."
That sentiment was echoed by a number of IP vendors: True Circuits Inc. (Palo Alto), which has made a successful practice with phase-locked loops; Qualcore Logic Inc. (Sunnyvale, Calif.), whose analog IPs include data converters, serdes, physical layers and other I/O; and LTrim Technologies Inc. (San Jose, Calif.), which markets power-management devices.
While power-management devices like three-terminal low-dropout regulators are as close to a drop-in analog IP as one can find, customer hand-holding-especially for analog-is inevitable. The IP business will always have a service orientation, reminds Mike Shamshirian, LTrim's business development vice president. "If you don't service, you don't have a business."
"Services and hand-holding will always be required [for analog property trade]," agreed Sandipan Bhano, CEO of Knowlent. "It's far from push-button, but an IP verification suite does take quite a bit of pain away."
Stephan Ohr (firstname.lastname@example.org) is technology editor for the EE Times Network and site editor for planetanalog.com.