'Spirit' consortium claims progress on IP tool

Spirit, which has enrolled major EDA vendors and European SoC developers, has undertaken a highly ambitious program to make IP not just reusable, but reusable with almost no engineering effort. This involves efforts by consortium members, with help from others who wish to produce Spirit-compliant IP or tools.

The heart of the program is an electronic datasheet, an XML document that encapsulates, in a tool-independent form, the design intent, structure, connectivity and protocol information necessary to integrate a piece of IP into an SoC. The information is embedded in a number of schemas that specify components, connectivity, meta-data about the requirements the IP will impose on the platform into which it is integrated and bus definitioins.

A second major effort left mostly to tool developers is the creation of generators that produce useful files or tools for IP integration, based on the information in the XML documents. Examples are generators to produce connection netlists, transaction-level models for verification, full test benches with timing requirements or configuration files for the IP itself.

Spirit technical chairman Chris Lennard gave a progress report on the incremental, and some have said grindingly slow, rollout of the technology. Lennard said there have been more than 1,000 downloads of the Version 1.0 Spirit document released last December. Version 1.1, Lennard said, is basically a "hardened" version of the Version 1.0 deliverables, with the addition of a mechanism for including timing constraints, based on a donation from Synopsys. Version 2.0, which Lennard said "will cover all verification and implementation languages at the transaction and structural description level," is scheduled for release in December.

Lennard was quick to emphasize that although future releases would add significant capability to Spirit, "We are enabling design today with these tools, not waiting for the next release."

Demonstrations at the Design Automation Conference show here indicated that tool vendors are, in at least some cases, taking Lennard's enthusiasm to heart, demonstrating Spirit-compliant tools in at least alpha form. But the heaviest use of the technology so far appears to be within Philips Semiconductors, which has based an entire SoC automated IP assembly flow on the Spirit databooks.

Mentor Graphics, which donated the schema which became the basis of the XML description, applauded the progress. Synopsys announced a Spirit-compliant tool and IP shipments. ARM Ltd. asserted that version 1.1 was ready to use, adding that they would include Spirit compliance in its RealView MaxSim tool in the second half of 2005, and were constructing a generator that would create an AXI interconnect fabric from the schemas.

ST Microelectronics said there were three production ICs in design using a Spirit-based flow, involving about a hundred IPs. Meanwhile, Philips claimed two chips under development as evaluations of their automatic flow. Both are dense ARM-11-based SoCs at the 65-nm node.

Spirit chair Ralph von Vignau said plans to launch the technology and then hand it over to an existing standards body had been temporarily delayed.

Asked about savings resulting from the use of Spirit, various developers offered numbers ranging from a 20 percent savings in engineering time, if much of the chip is newly-developed, to 90 percent if the chip is based largely on existing configurable IP.