SUNNYVALE, Calif.--(BUSINESS WIRE)--July 11, 2005
--Synplicity Inc., a leading supplier of software for the design and verification of semiconductors, today announced the 5.0 version of its Amplify RapidChip and Amplify RapidChip Pro software, an enhanced solution within its Amplify family of customized physical synthesis software. The Amplify RapidChip software, which was uniquely developed for LSI Logic's RapidChip platform ASIC devices, features several new optimizations that deliver higher quality of results and enable users to perform fast timing closure for their RapidChip device. The latest version of the Amplify RapidChip Pro software offers customers a combined physical synthesis and floorplanning solution that provides significant performance and time-to-market improvements for designers utilizing LSI Logic's RapidChip Platform ASIC devices. New features in the Amplify RapidChip Pro software include an advanced macro placer and the Affinity Placer(TM).
For more than two years, Synplicity has worked closely with the major structured/platform ASIC vendors to develop customized synthesis and physical synthesis software that targets the individual vendor's unique architecture. Through such collaboration, Synplicity has become the primary EDA tool provider of architecture-specific implementation tools for this growing market. The customized physical synthesis solutions Synplicity jointly developed with the vendors offer users several advantages over conventional ASIC design flows, including enabling a one-pass hand-off to the structured/platform ASIC vendor. The Amplify software enables users to reduce their entire structured/platform ASIC-based design time by up to one-half, compared to traditional ASIC flows.
"We share a common mission with LSI Logic to enable designer productivity and speed time to market," said Andy Haines, vice president of marketing, Synplicity. "Synplicity has worked closely with LSI Logic's RapidChip engineering team for more than two years to create a customized physical synthesis solution that uniquely targets the RapidChip architecture and sets a new standard for custom logic designer productivity. We believe that RapidChip customers using Synplicity's Amplify RapidChip software will receive an easy-to-use streamlined design flow that will help them achieve the results they have come to expect from Synplicity."
Key Technology Innovations Within the Amplify RapidChip Pro Software
The Amplify RapidChip Pro software offers an enhanced macro placer that automatically and efficiently places small macros and memory blocks within LSI Logic's RapidChip architecture. The new enhanced macro placer within the Amplify RapidChip Pro software reduces the need for customers to manually floorplan the memory and macro blocks within the RapidChip device, while also minimizing design iterations. The result is users are able to converge on timing closure much quicker and obtain excellent quality of results. Synplicity has found that by using the new macro placer total wire length (TWL) for routing, the design can be reduced up to 18 percent, providing significant timing and congestion improvements in the design.
Also in the latest version of Amplify RapidChip Pro is the new Affinity Placer. The Affinity Placer provides users a pre-placement constraint mechanism to keep conflicting paths from interfering with each other's performance. The Affinity Placer can yield significantly higher quality of results for circuit placement in RapidChip Platform ASIC devices, specifically to manage timing closure for designs using the RapidChip technology advanced high speed I/Os.
"Our RapidChip platform ASIC devices have an innovative architecture that provides design flexibility with excellent performance and low power consumption," said Ameesh Desai, senior director of design technology, LSI Logic Corporation. "We've worked very closely with Synplicity to ensure that Amplify RapidChip has the detailed knowledge of our architecture that is required for creating performance-optimized platform ASIC solutions. We believe the enhancements to the Amplify RapidChip software will further enhance our customer's ability to achieve rapid timing closure and significantly reduce manual floorplanning."
The Amplify RapidChip Pro software features several other enhancements that improve quality of results for RapidChip devices, while improving overall area and placement utilization. These enhancements include support for LSI Logic's memory architecture and a RapidChip device-specific floorplan input checker.
Additional Innovations in Amplify RapidChip
The Amplify RapidChip and Amplify RapidChip Pro software both offer additional capability to accelerate closure of complex RapidChip designs. LSI Logic's latest slices contain an advanced memory architecture for which the Amplify RapidChip software has been customized to achieve optimal results in floorplanning, physical synthesis, and placement. The design flow now has a seamless transfer of information from the RapidWorx® memory selector to Amplify RapidChip. The floorplan input checker validates the input and makes sure it is a "legal" floorplan before committing it to physical synthesis. This feature enables users to catch design problems much earlier in the design flow and reduce the number of iteration.
The Amplify RapidChip Pro software is available now. For more information, visit Synplicity at http://www.synplicity.com.
About Synplicity's Amplify Family of Structured/Platform ASIC Products
The Amplify family of structured/platform ASIC products includes customized design tools that provide a one-pass placed gates handoff. These tools directly target and understand each unique structured/platform ASIC architecture and typically enable 15-20 percent speed and area improvements over conventional design flows, thereby bringing results much closer to that of standard-cell ASICs. The physical synthesis tools also solve the timing closure problem by being fully integrated and correlated to the structured/platform ASIC vendors tools. The combination of Synplicity tools and the vendors' pre-verified architectures automatically solves problems for ASIC designers such as design for test, power distribution, clock distribution, signal integrity, and manufacturability. Earlier this year, Synplicity's family of platform/structured ASIC products received the 2005 DesignVision Award, which recognizes technologies, applications, products and services judged to be the most unique and beneficial to the industry.
Synplicity® Inc. is a leading supplier of innovative synthesis, verification and physical implementation software solutions that enable the rapid and effective design and verification of semiconductors. Synplicity's high-quality, high-performance tools significantly reduce costs and time to market for FPGA, structured/platform ASIC and cell-based/COT ASIC designers. The company's underlying Behavior Extracting Synthesis Technology® (BEST(TM)), which is embedded in its logical, physical and verification tools, and has led to Synplicity's top position in FPGA synthesis, now provides the same fast runtimes and quality of results to structured/platform ASIC, cell-based ASIC and COT customers. The company's fast, easy-to-use products support industry standard design languages (VHDL and Verilog) and run on popular platforms. Synplicity employs over 280 people in its 20 facilities worldwide. Synplicity is headquartered in Sunnyvale, California. For more information visit http://www.synplicity.com.
This press release contains forward-looking statements including, but not limited to, statements regarding the performance and achievements of Synplicity's Amplify family of structured/platform ASIC synthesis tools and the position of Synplicity in the structured/platform ASIC market. In some cases, you will be able to identify forward-looking statements by terminology such as "may," "will," "should," "expects," "believes," "can" or the negative of these terms or other comparable terminology. These statements are only predictions and involve known and unknown risks, uncertainties and other factors that may cause the forward-looking statements and Synplicity's results to differ materially, including the performance and benefits of Synplicity's software relative to relevant industry methods or standards, design flaws, design difficulties or other problems with the Amplify software and the growth and changing technical requirements in the platform ASIC market. For additional information and considerations regarding the risks faced by Synplicity, see its annual report on Form 10-K for the year ended December 31, 2004 as filed with the Securities and Exchange Commission, as well as other periodic reports filed with the SEC from time to time, including its quarterly reports on Form 10-Q. Although Synplicity believes that the expectations reflected in the forward-looking statements are reasonable, Synplicity cannot guarantee the future performance or achievements of its software. In addition, neither Synplicity nor any other person assumes responsibility for the accuracy or completeness of these forward-looking statements. Synplicity disclaims any obligation to update information contained in any forward-looking statement.
Synplicity, Amplify and Behavior Extracting Synthesis Technology are registered trademarks of Synplicity Inc. BEST is a trademark of Synplicity Inc. All other brands or products are the trademarks or registered trademarks of their owners.