Axeon has working silicon of Learning Processor

Axeon has working silicon of Learning Processor
By Peter Clarke, EE Times
November 8, 2000 (2:50 p.m. EST)
URL: http://www.eetimes.com/story/OEG20001108S0009

LONDON — Two-year-old startup Axeon Ltd. (Aberdeen, Scotland) has received working silicon from its foundry of the "Learning Processor," an array of 256 RISC processors, and is ready to start benchmarking the device, the company said.

After delays with faulty first-time silicon, Axeon will test the Learning Processor in a channel equalization application for 3G communications.

Although this is Axeon's initial goal, and one for which it has successfully just closed a funding round worth about $5 million, the company claims the technology is suitable for other applications as diverse as inertial navigation and automated image analysis.

Axeon is now able to supply development boards based on a Learning Processor array implemented in a 0.6-micron CMOS process technology together with an array controller and I/O system contained in a separate FPGA. In its current implementation, the Learning Processor is a n array of 256 8-bit RISC processors that operate at 50 MHz. The maximum clock frequency is expected to scale up to about 500 MHz as the array design is recast in 0.18- and 0.13-micron CMOS.

As the clock frequency increases the die area required for the array will shrink, reducing the cost of discrete packaged devices and the area on a system-chip taken up by the Learning Processor, the company said.

The processor is based on theoretical work on self-organizing maps written by Neil Lightowler while he was a graduate student at Aberdeen University. Lightowler is a cofounder and chief technology officer of Axeon.

"Having working silicon allows us to build an application demonstration," said Hamish Grant, founder and chief executive officer of Axeon.

Grant said Axeon would eventually offer both the array and its controller as soft intellectual property (IP) defined at the register transfer level. "Both elements will be sold as an IP core to be integrated within a baseband chip," he said.

Gra nt had said in September 1999 that Axeon planned to have silicon that same year, but the silicon "didn't work right first time," he said. "But we got it to work second time around. It means we've spent two years in the development cycle rather than 18 months."

Despite the delay, backers have returned to fund a second round. And the extra time has also convinced Grant of the market opportunity for the Learning Processor in 3G communications.

"The operating companies are saying the technology is not yet there; that early terminals will operate at just 56 kbits/second rather than the 2 Mbits/second the standards allow for," he said. "People are struggling to design receivers. But our array will effectively replace the rake receiver in such a terminal."

Grant said the early test results support the technology's ability to realize the bandwidth rate promised, but as yet unachieved, by 3G communications developers. The Axeon solution should not only deliver the necessary functionality but do so in a small area and with low power consumption, the company said.