MIPS, ARM pushing RISC/DSP cores in Taiwan

Reckoning that more than 50 percent of commonly executed DSP tasks are modestly complicated, MIPS believes that much of this work can be handled in a high performance RISC-based host processor with DSP instruction sets, such as multiplier-accumulator (MAC).

“Over time you see more and more applications moving over into this space,” said Chris Cavigioli, MIPS’ market development manager for multimedia, during the Embedded Systems Conference-Taiwan. “We see applications in audio, such as music decompression in MP3 players, voice-over-IP, which is typically the speech coding algorithms, and fax and data modem algorithms and JPEG image decompression.”

Bringing together the worlds of RISC and DSP is nothing new. But as notions like the “digital home” and “connected computing” begin to gain traction, demand for devices to carry out complex control and signal processing intensive tasks is growing. Taiwan hopes to be at the forefront of the convergence between the PC realm and the consumer electronics world where these devices will operate.

But working with both RISC and DSP architectures poses some programming difficulties for developers. First, they often must juggle distinct development environments: While RISC devices are control-oriented and C-friendly, DSP engines require difficult, data- and math-intensive machine code "inner loop" programming. In addition, code development must be done in a heterogeneous multiprocessor environment, with at least two or more compute elements.

In its approach to combining the functions, Cavigioli said MIPS is not out to create the world’s best DSP, but simply to offer what’s good enough. With a die penalty of about 3 percent, he said MIPS can double its performance of real-time signal processing tasks and capture about 80 percent of the more commonly executed, less intensive DSP tasks.

Because of increasing system complexity, stemming from a need to handle more intensive algorithms, for instance, and also due to the need to meet the demand for lower development costs, designers are using RISC/DSP engines. “Now if you look at RISC with DSP versus a single processor, a dedicated signal processor can offer better performance. But a RISC with a DSP capability can give you much greater flexibility and greater ease of design reuse and also faster time to market,” said John Cornish, marketing vice president of ARM's Processor Division.

ARM’s approach also includes adding DSP instructions, including MAC, and single-instruction, multiple-data (SIMD). Cornish said ARM’s next-generation cores will include a hybrid 64- or 128-bit SIMD architectures and include integer and single precision floating point capability, which will be important for high performance multimedia applications.

— Bernard Cole, editor of Embedded.com, contributed to this report.