NURLOGIC BUILDS UPON ANALOG DESIGN EXPERTISE WITH INTRODUCTION OF HIGH-PERFORMANCE, LOW-VOLTAGE OFFERING OF SPECIALTY I/Os
NurLogic's 0.18- and 0.15-micron specialty I/Os meet customers' challenging design parameters, provide significant time-to-market savings and offer increased reliability
SAN DIEGO - November 06, 2000 - NurLogic Design, Inc., a privately held, high-growth, semiconductor technology and intellectual property (IP) company, today announced the availability of a complete family of specialty I/Os optimized for 0.18- and 0.15-micron process technologies. These standard bus interface I/Os are ideally suited for communications, memory and graphics applications. NurLogic's family of specialty I/Os significantly reduces customers' design time and provides a high-performance, low-voltage solution for analog-intensive I/O functions.
Process-optimized for each foundry, NurLogic's 0.18- and 0.15-micron families of specialty I/Os include LVDS for signaling and implementing GHz-level communications; PECL for differential I/O and clocked outputs; SSTL for high-speed GUI interfacing; HSTL for communications; and DDR for double date rate DRAM interfacing. The 0.18- and 0.15-micron specialty I/Os are completely compatible with NurLogic's standard I/O offerings, which support a variety of drive strengths and I/O control functions.
"NurLogic's introduction of the 0.18- and 0.15-micron specialty I/O families demonstrates our ability to efficiently manage the challenges associated with specialty I/O design and supports our commitment to create a solid bridge between customer design objectives and reliable process-tuned solutions," said Michael Brunolli, NurLogic's chief technical officer. "By leveraging our core competencies in analog design, we provide a complete line of specialty I/Os that enhance the designer's selection of robust IP solutions, while allowing for the quick and reliable deployment of low-voltage and high-performance functions."
These high-end specialty I/Os present many design challenges which internal development teams do not always have the expertise or time to address. Design issues include the need to meet varying standards and customer applications, which is further complicated by the large variations between the fast and slow process corners. These specifications can be met using analog circuit design techniques, which NurLogic has developed, including good impedance matching and termination up to GHz frequencies.
AVAILABILITY The complete 0.18-micron specialty I/O family as well as the LVDS, PECL and SSTL 0.15-micron specialty I/Os are currently available from NurLogic. The HSTL and DDR 0.15-micron specialty I/Os are scheduled for release next quarter. For pricing information, please contact us at 1-877-NURLOGIC.
ABOUT NURLOGIC DESIGN, INC. NurLogic Design, Inc. provides a broad range of semiconductor technology products, including Foundation IP, such as standard cell libraries, specialty I/Os and embedded memory cores; higher level analog and mixed signal IP cores; SOC Design Services and ASSP design. NurLogic is a privately held corporation headquartered at 9710 Scranton Road, Suite 380, San Diego, CA 92121. Further information on NurLogic can be found on the web at www.nurlogic.com or by calling 1-877-NURLOGIC.