| Fremont, Calif. The block diagrams for most moderate-sized systems-on-chip look just about the same. You have your CPU, a local bus with cache, a DRAM controller and maybe an accelerator, a bridge and a peripheral bus with a bunch of I/O controllers, ranging from simple programmable I/O pins to fairly complicated blocks. If you could just change one or two blocks to fit particular customer needs, you could cover a huge range of applications with one piece of silicon. |
That observation has not escaped chip vendors. As far back as the Motorola 6805 family, chip makers have attempted to make MCU peripherals as interchangeable blocks, so that any combination could simply be dropped into a design flow. But with the growing complexity of intellectual-property integration at finer geometries, this approach has become too expensive for less-than-stellar opportunities, even with proven IP.
Now, STMicroelectronics believes it has another alternative that will be particularly valuable to some customers. Combining the eASIC single-mask-configurable fabric with an ARM9, ST's Structured Processor Enhanced Architecture, or Spear, chip, which just began sampling, provides a basic background set of peripherals and memory and then gives the customer the opportunity to insert up to about 400,000 gates of IP.
The basic layout of the chip is absolutely vanilla: a 192-MHz ARM 946 core with instruction and data caches, an AHB bus with three USB 2.0 ports and a 10/100 Ethernet media-access controller, an interface to off-chip memory and an APB bus gathering up a host of low-speed I/O devices, including an A/D converter.
The unique thing about the chip is the eASIC fabric. The block is provided with connections to the AHB, directly into the CPU core via the coprocessor port, and to its own I/O pins. The fabric allows implementation of up to 400k equivalent ASIC gates of logic or SRAM, at a speed that lets circuits in the fabric clock at the ARM's 192-MHz rate. Thus, customers can configure the fabric to implement either peripheral blocks or closely coupled accelerators, or both.
ST is providing two stages of development and debug support for the chip. At the simulation stage, the company supplies full netlists, so customers can simulate the full chip, including their own logic configurations. For hardware prototyping, there is a debug mode that can multiplex the AHB-to-I/O pins at reduced speed, naturally so that an external FPGA can be used to prototype the functions in the configurable fabric.
Once the customer is happy with a design, ST will implement a single wafer, using its e-beam configuration capability, and provide samples in a matter of weeks. Full production requires only the creation of a single via mask based on the customer's netlist.
Offering an alternative at essentially cell-based performance, density and power, but with turnaround times and customization charges near those of FPGA-based alternatives, the Spear may extend the reach of standard-product systems-on-chip further into the applications that previously, because of their volumes or time-to-market requirements, had to settle for FPGA solutions.