MILPITAS, CA, Aug. 3, 2005
AccelChip Inc., the industrys only provider of automated flows from MATLAB algorithms to silicon, today announced the immediate availability of its 2005.3 version of AccelChip DSP Synthesis and AccelWare intellectual property (IP) toolkits for model-based design of digital signal processing applications.
New to the AccelChip DSP Synthesis tool is a feature that allows for pipe-line insertion to increase design performance while lowering chip power. The company has also added enhancements to the tools automated floating-point to fixed-point conversion utility that improves fixed-point simulation performance up to 100% percent. In addition, updates have been made to all third-party tool integrations to ensure interoperability. New and enhanced AccelWare cores extend the companys leadership position with DSP cores that directly implement matrix operations in markets such as communications, signal intelligence, electronic warfare, radar, and sonar.
Model-based design enables engineers to quickly evaluate multiple design options by testing and optimizing their algorithms in the Simulink modeling environment before they deploy them in an embedded system, reducing design time and development and implementation costs, said Ken Karnofsky, marketing director for Signal Processing and Communications at The MathWorks, Inc. AccelChip DSP Synthesis and AccelWare can complement The MathWorks Model-Based Design solutions by providing a direct path to FPGAs and ASICs.
The combination of algorithm synthesis and DSP IP is critical to rapid design space exploration, added Michael Bohm, AccelChips CTO and vice president of product development. While traditional RTL synthesis tools have allowed area and frequency tradeoffs, AccelChip enables system-level tradeoffs, such as sample rate, latency, error, power, area and frequency. The 2005.3 release extends the achievable design space with improved overall performance, new high speed and streaming I/O micro-architectures for FFTs, as well as enhancements to our Cholesky matrix inverse core that detect non-invertible matrices.Enhanced Tool Flow
To provide DSP algorithm and hardware developers with a compressive and verified Model-Based Design flow from MATLAB to silicon, AccelChip partners with EDA and FPGA vendors to provide an integrated DSP design environment. AccelChip has built a unique test environment that features over 6000 circuits and verifies all tool combinations to ensure interoperability.
AccelChips testing environment is very comprehensive, said Misha Burich, senior vice president, software and systems engineering at Altera. The AccelChip team consistently provides Altera with valuable feedback on our Quartus II development software. It is because of the tight cooperation between the two companies that we have accepted AccelChip into our ACCESS partner program.
The 2005.3 release of AccelChip DSP Synthesis has been certified to support the most current production version of Aldec Riviera, Altera Corporations Quartus II development software, Cadence NC-Verilog and NC-VHDL, Mentor Graphics ModelSim, LeonardoSpectrum and Precision RTL Synthesis, Synplicity Synplify Pro, Synopsis Design Complier and Design Complier FPGA, The MathWorks MATLAB and Simulink, and Xilinx ISE and System Generator for DSP. Pricing and Availability
Version 2005.3 of AccelChip DSP Synthesis and AccelWare IP Toolkits is now shipping. Current AccelChip customers on support will receive the new release at no additional fee. For more information on AccelChip DSP Synthesis and AccelWare IP, please email email@example.com.About the Company
AccelChip Inc. is the industrys only provider of MATLAB-based algorithmic synthesis solutions, including DSP intellectual property (IP), for embedded DSP design. The company develops and markets design tools, integrated verification flows, and parametric IP toolkits that combine to automate the development and implementation of DSP algorithms in FPGAs and ASICs. AccelChips proven solution integrates the domain-specific DSP design environment (MATLAB) with industry-standard hardware design flows from Aldec, Altera, Cadence, Mentor Graphics, Synplicity, Synopsys, The MathWorks, and Xilinx. Founded in 2000, AccelChip is located in Milpitas, California, and has design centers in Portland, Oregon, and Carlsbad, California. AccelChips Web address is www.accelchip.com
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AccelChip, AccelWare, and AccelView are registered trademarks of AccelChip Inc. All other trade names referenced are the service marks, trademarks, or registered trademarks of their respective companies.