| EE Times met with Carl Schlachte (shown left), chief executive officer of ARC International plc, in London at the end of one of his visits to ARC’s base in Elstree. Peter Clarke asked Schlachte how things are going for ARC, a small but innovative listed company in the crowded processor IP space. |
EE Times: ARC was able to raise a lot of money with a fortuitously-timed IPO at the peak of the dot com boom. Things have been tougher since then and profits elusive. How much cash do you have left and what’s the burn rate?
Schlachte: £33 million (about $60 million) and £500,000 in the last half (about $890,000). Under London Stock Exchange rules I am not allowed to make forecasts of revenue or profitability but I can say I am very optimistic about the second half of the year.
EE Times: But revenue has been going down?
Schlachte: We sold off some activities, but on a like-for-like basis our revenue was up 10 percent. For 2004 over 2002 revenue was up 40 percent.
EE Times: Is revenue still mainly licence fees rather than royalties?
Schlachte: We have signed 103 licenses with 50 signed in the last 18 months. I think the most recent numbers showed about 22 percent of revenue from royalties and 65 percent from license fees.
EE Times: Your previous answers indicate you think there is life in the IP business model. Some have argued that there are only one or two successful IP companies and that there is not really room for multiple companies offering processor IP.
Carl Schlachte: Yes, I think the model works. We’re picking up ground on MIPS. But I do think the market is set to undergo a substantial change. It’s interesting to note that all the main IP processor players claim a configurable offering as part of their portfolio.
The progression has been CISC to RISC to configurable CPU. But many of today’s RISC processor architectures are bloated and old. The companies are asking people to make a number of sacrifices to preserve compatibility with the past.
Configurability is one way round that.
EE Times: Argonaut RISC Cores, which became ARC, was one of the first companies to implement a user-configurable instruction-set CPU. But you have patent coverage. Why are you letting ARM, MIPS and Tensilica do your thing?
Schlachte: You can’t prosecute without patents. We’ve had patents pending for seven years. I am not sure why it has taken so long but we had another batch of patents granted in March. “The ‘563 patent [U.S. patent number 6,862,563] is important. There’s 14 more that have been granted. And we have 44 patents pending.
ARM and MIPS endorsing configurability is a good thing. But we have a duty to investors to protect our position. We vigorously defend our intellectual property but we prefer to work with all companies to endorse configurability. We are, after all, an intellectual licensing company.
EE Times: I don’t know of any lawsuits. Are you in discussions with any or all of your processor IP rivals, or would you prefer not to have your patents tested?
Schlachte: No comment.
EE Times: Apart from configurability, there is another sense in which digital data processing has entered a new era multiprocessing. What is ARC doing to address this?
Schlachte: One thing we are doing is to offer customers complete subsystems for a particular application based around an ARC core plus additional processing hardware and the software, such as our ARCsound system. When that interfaces with a host processor, it is a form of heterogeneous multiprocessing.
EE Times: Offering a software level solution is also important but I was thinking of offering multiple ARC cores in the same manner that ARM is offering a multiprocessor core.
Schlachte: Ah, you mean symmetric multiprocessing. We can’t do it at the moment but we are focusing on the applications where we have a chance to achieve high volume. It’s not what those people are interested in. They want to save cost. They want to save it through time-to-design, They want to save it through saving the die area of each system-chip.
We often see them putting extra instructions into our processor which adds to the processor area but they show us how a single instruction can save a lot of on-chip memory, which could be 50 percent of the die area.
We’ll support symmetric multiprocessing if the volume guys start asking for it.
EE Times: What about China and the far-east. For many high volume products that is where the manufacturing is? ARM and MIPS seem to have been active over there although protecting intellectual property in China is notoriously difficult.
Schlachte: We want to do something in China. We have offices in Taiwan and Japan and representation in every other Asian territory, except China. Look to us to change that before the end of the year.