FRONTIER DESIGN UNVEILS SPEECH IP STRATEGY Plans for Highly Integrated, Ultra Low Power, Low Cost Solutions for VoIP, Mobile Phones, and Command & Control Applications
NOVEMBER 2, 2000, SPEECHTEK 2000, BOOTH 2006, NEW YORK, NEW YORK -- Frontier Design today announced its plans to offer a broad range of speech technology intellectual property solutions that address the needs of applications in the areas of VoIP, mobile and cordless telephones, toys, games and command and control.
The firm has already created an arsenal of speech related intellectual property that includes algorithms for speech recognition and synthesis, speech compression/decompression, DTMF detection and generation, and echo cancellation, as well as C-language executables and HDL cores of those algorithms that can be implemented in FPGAs or ASICs.
The company's speech recognition and synthesis (SRS) core, introduced last October, has the highest accuracy of any speaker-dependent core on the market today and has been used in the design of a variety of voice activated products including mobile phones and calculators.
Frontier Design has mapped the SRS core onto National Semiconductor's CR16B RISC base-band processor for DECT wireless phones. ASCOM of Switzerland has recently introduced a DECT phone based on National's chipset that uses Frontier Design's SRS implementation for voice-dialing.
Silverline, Ltd. has licensed Frontier's SRS ASIC implementation for its line of voice activated gift products.
Frontier Design's recently introduced (October 23, 2000) ADPCM speech compression IP core has already been licensed by two major mobile phone manufacturers, a leading DSP and ASIC vendor, and a leading supplier of VoIP chips for telephony over DSL and cable-based networks. Frontier's ADPCM provides the lowest silicon and per channel IP cost of any ADPCM cores on the market today. Frontier offers shrink-wrapped implementations for ASIC and Xilinx FPGA of up to several thousands of ADPCM channels.
Herman Beke, Frontier Design's CEO said "Without actually forming any intent, our engineers have developed some of the most powerful speech technology on the market today. Everything we have done in this area has had excellent performance, cost and power consumption characteristics and has been very well received. As a result, we have decided to formalize our position in this market and put more resources behind it.
"There is a huge need for low cost, low power solutions in the speech area. Doing speech recog-nition on a 800+ MHz Pentium III is pretty easy because you have the horsepower to do almost anything you want. However, the cost and the power consumption of Pentium processors or even DSP processors are too high for them to have any application in cost-sensitive, hand-held consumer products like mobile phones, remote controls, or Internet appliances. This is where our solution comes in. Our speech recognition and synthesis core takes only five to ten MIPS of processing on National's CR16B RISC processor. Originally this algorithm required a 400 MHz Pentium. Our engineers managed to fit it in a 15,000 gate system-on-a-chip that has 5 MIPS of throughput, a clock of only 2 MHz and an average word recognition latency of only 250 ms. The SoC consumes only 6 uA in standby and 16 mA during speech recognition and synthesis, while also driving the speaker. That's quite an accomplishment.
"With the heat on to increase highway safety by allowing hands-free only mobile phone use in automobiles, voice control of the phone will become a mandatory feature," Beke explained. Our core is the only one that delivers the low power and low cost required to meet the pricing and battery life considerations of mobile phone users.
"Our new ADPCM speech compression core is another low power, high throughput solution. With a clock of just 8 KHz per channel for full-duplex compression and decompression, it is also an exceptionally low power solution for Internet phones, PDAs, cellular phones and other hand-held speech appliances. The multi-channel version of this core offers telephone equipment vendors as many as 6,000 ADPCM channels in only 32,000 ASIC gates or 1024 channels in a Virtex XCV600E. This is by far the lowest silicon cost of any multi-channel ADPCM core on the market today," Beke emphasized.
"Our product roadmap includes the further development and optimization of our existing cores and the further development of our algorithms for echo cancellation and DTMF detection and generation. All our cores are C-language based and can be compiled for execution on processors or DSPs, and as Verilog or VHDL cores for both cell-based ASIC and FPGA implementation. This is an area where we see great promise and toward which we will commit significant resources in the development of optimized speech technology solutions." Beke concluded.
Frontier Design was founded in 1997 as the result of a management buy-out of the European Development Center of Mentor Graphics (NASDAQ: MENT). The firm's primary emphasis is its "algorithm-to-silicon" design methodology that greatly improves the creation of Silicon IP blocks starting from customer- proprietary or industry-standard algorithms in the fields of wireless telecom, consumer audio or multimedia applications. Algorithm-to-Silicon IP blocks consume less power, are less costly and require substantially less development time than other alternatives. Frontier Design sells its design services and a line of EDA tools directly from its facility in Leuven, Belgium, and from its sales office in California. Frontier Design also sells through a growing number of distributors and Value Added Resellers in Northern America, Europe, Japan and the Pacific Rim. Frontier Design's World Wide Web site is http://www.frontierd.com. Email inquiries may be sent to firstname.lastname@example.org.