Enabling single-chip system control and audio signal processing for digital audio products, and providing digital audio solutions including various kinds of middleware
Tokyo, August 9, 2005 −− Renesas Technology Corp. today announced four SH7261 high-performance microcontroller models, incorporating the 32-bit RISC (Reduced Instruction Set Computer) microcontroller SuperH™*1 Family's new SH2A-FPU CPU core, for use in car audio, home audio, and similar digital audio products. Sample shipments will begin in September 2005 in Japan.
These new devices are high-performance microcontrollers incorporating peripheral functions suitable for car audio and home audio systems, including a CD-ROM decoder, CAN controller*2, and serial sound interface.
These new microcontrollers offer the following features.
|(1) ||High-performance CPU core with built-in FPU, offering system control and audio processing with a single chip |
| ||The new SH2A-FPU CPU core features the addition of an FPU (floating point number processing unit) to the excellent real-time control capabilities of the SH-2A CPU core. Two versions are available, with a maximum operating frequency of 80 MHz and 120 MHz respectively. Operation at 120 MHz provides high processing performance by integer operation performance of 288 MIPS (million instructions per second) (Dhrystone 1.1) and floating-point operation performance of 240 MFLOPS (mega floating point number operations per second). |
Processing previously performed by two devices — a system control processing controller and a digital audio processing DSP or the like — can thus be handled by a single SH7261 microcontroller, enabling the number of component parts to be reduced and lower system costs to be achieved.
|(2) ||On-chip peripheral functions including CD-ROM and CAN controllers suited to digital audio and industrial products |
| ||The SH7261 microcontrollers have an on-chip CD-ROM controller implementing CD player playback functions, enabling CD-ROM support functions to be configured with inexpensive external components. |
Data communication functions are provided by a 2-channel in-vehicle LAN CAN controller in the SH72611 and an IEBus™ controller*3 in the SH72612, offering users a choice of models appropriate to car audio, industrial, or other applications. The comprehensive set of on-chip peripheral functions also includes serial communication functions such as a serial sound interface (SSI) for digital audio data input/output, a serial communication interface with a 16-stage FIFO, and an I2C bus*4 interface, as well as a multifunction timer unit (MTU2)*5, 10-bit A/D converter, and 8-bit D/A converter useful for various kinds of industrial applications.
|(3) ||Software solutions provided by a variety of middleware |
| ||Middleware compatible with various audio formats is available, including MP3, WMA, and AAC (Advanced Audio Coding). The high processing performance of the CPU core enables multi-CODEC support to be implemented by software, providing software solutions for digital audio products. |
Fields such as car audio and home audio are witnessing increasing popularity of high-value-added products equipped with audio data playback functions compatible with various compression standards, functions for recording audio CD music data on an HDD (hard disk drive) in compressed form, and so forth. In line with this trend, devices equipped with audio data compression/expansion functions are becoming more widespread, but digital audio processing has up to now been performed by DSPs, dedicated LSIs, and the like. However, in order to further lower the cost of user products, there is a strong demand for a reduction in the number of component parts by incorporating digital audio processing functions in the microcontrollers hitherto used for system control.
Renesas Technology has previously released products incorporating a 16-bit CISC CPU core as system control microcontrollers for car audio and home audio systems, and these have captured a major share of the market.
Now, in response to market demand, Renesas has developed the high-processing-performance 32-bit SH2A-FPU CPU core, and SH7261 microcontrollers incorporating peripheral functions suitable for digital audio systems, that enable system control and digital audio processing to be implemented with a single chip.<Product Details>
These new SH7261 microcontrollers incorporate a newly developed high-performance SH2A-FPU CPU core with a built-in FPU. Versions with an 80 MHz and 120 MHz maximum operating frequency are available. Operation at 120 MHz provides high processing performance by 288 MIPS integer operation performance and 240 MFLOPS floating-point operation performance, further improving on the signal processing performance of the existing SH-2A CPU core.
The instruction set is upward-compatible with those of the SH-2A and earlier SH-2 CPU cores, enabling existing programs to be used while improving ROM code efficiency by approximately 75% compared with the SH-2, an improvement that makes it possible to reduce program size by approximately 25%.
These high signal processing capabilities enable MP3, WMA, AAC, and suchlike audio data compression/expansion processing to be executed at a lower frequency and by a smaller program. In addition, system control and digital audio processing previously performed by separate devices can be handled by a single SH7261 chip, enabling fewer component parts to be used. This makes it possible to implement a low-power-consumption system at low cost.
These microcontrollers also incorporate a variety of interfaces and peripheral functions necessary for configuring a digital audio product. The on-chip CD-ROM decoder enables CD-ROM playback functions to be implemented simply by adding inexpensive external parts, helping to achieve significantly lower system cost.
In addition, to (1) a 2-channel CAN controller in the SH72611 and (2) an IEBus™ controller in the SH72612 as functions for data communication with other devices within a user end-product, the comprehensive set of on-chip communication functions includes a 2-channel serial sound interface for digital audio data input/output, an 8-channel serial communication interface with a 16-stage FIFO, and a 3-channel I2
C bus interface.
An external data bus expandable up to 32 bits allows direct connection to flash ROM, SDRAM, SRAM, and so forth, without the use of external parts.
Other on-chip functions include an 8-channel multifunction timer unit suitable for motor control, capable of 3-phase PWM wave output for AC motor control, as well as an 8-channel 10-bit A/D converter, 2-channel 8-bit D/A converter, and 8-channel DMAC. These varied peripheral functions enable the number of external parts to be reduced, and make it possible to create a high-performance system at lower cost.
MP3, WMA, AAC, or similar audio compression standard compatible middleware enables a multi-codec-enabled system to be implemented by software, while software including CD-ROM ISO9660 file system and HDD FAT32 file system software is also available, providing software solutions for digital audio product development.
The package is a 176-pin LQFP.
On-chip debugging functions*6
are provided, enabling real-time debugging to be carried out at the maximum operating frequency. For the development environment, the USB bus-powered E10A-USB requiring no external power supply can be used as an emulator.
Renesas Technology will continue to develop products offering higher speed, performance, and functionality in line with market needs, developing a high-speed version with a 200 MHz operating frequency, improving performance through the use of multiple CPU cores, and implementing further peripheral function enhancements including provision of CD servo control functions and a USB interface.
|Notes: ||1. ||SuperH is a trademark of Renesas Technology Corp. |
|2. ||CAN (Controller Area Network): A network specification for use in vehicles, proposed by Robert Bosch GmbH of Germany |
|3. ||IEBus (Inter Equipment Bus) is a trademark of NEC Electronics Corporation. |
|4. ||I2C bus (Inter IC Bus): An interface specification proposed by Royal Philips Electronics of the Netherlands |
|5. ||MTU2 (Multi Function Timer Pulse Unit 2): A multifunction timer comprising six 16-bit timer counter channels, with maximum 16 pulse input/output and 3 pulse input capability |
|6. ||On-chip debugging functions: Part of the debugging circuitry previously incorporated in an emulator. Providing these functions on-chip enables simple emulation using the actual device for system evaluation. |
*Other product names, company names, or brands mentioned are the property of their respective owners.<Typical Applications>
<Prices in Japan> *For Reference
- Car audio : Car CD players, HDD-equipped car audio systems, etc.
- Home audio : Network audio, HDD-equipped audio systems, etc.
- Industrial equipment : Sequencers, robots, etc.
|Product Name || Type Name || Maximum Operating Frequency (Operating ambient Temperature) || On-Chip Controller || Sample Price |
[ Tax Included ] (Yen)
|SH7261 ||SH72611 ||R5S72611P80FPV ||80 MHz |
(-40 ºC to 85 ºC )
|CAN ||1,800 [ 1,890 ] |
|R5S72611C120FPV ||120 MHz |
(-20 ºC to 70 ºC )
|CAN ||1,700 [ 1,785 ] |
|SH72612 ||R5S72612P80FPV ||80 MHz |
(-40 ºC to 85 ºC )
|IEbus ||1,750 [ 1,838 ] |
|R5S72612C120FPV ||120 MHz |
(-20 ºC to 70 ºC )
|IEbus ||1,650 [ 1,733 ] |
Information contained in this news release is current as of the date of the press announcement, but may be subject to change without prior notice.
|Item || SH7261 Specifications |
|Product name ||SH72611 ||SH72612 |
|Type name ||R5S72611P80FPV ||R5S72611C120FPV ||R5S72612P80FPV ||R5S72612C120FPV |
|Power supply voltage ||3.3 V |
|Maximum operating frequency ||80 MHz ||120 MHz ||80 MHz ||120 MHz |
|Maximum processing performance ||At 80 MHz operation: 192 MIPS [Dhrystone 1.1], 160 MFLOPS |
At 120 MHz operation: 288 MIPS [Dhrystone 1.1], 240 MFLOPS
|Operating ambient temperature ||-40 ºC to 85 ºC ||-20 ºC to 70 ºC ||-40 ºC to 85 ºC ||-20 ºC to 70 ºC |
|CPU core ||SH2A-FPU |
|CPU instructions ||112 (including FPU-related instructions) |
|On-chip RAM ||32 Kbytes |
|Cache memory ||16 Kbytes (separate 8K instructions / 8K data, 4-way set associative type) |
|External memory ||Bus clock : Max. 60 MHz |
|SRAM, SDRAM directly connectable by bus state controller |
|Address space : 64 Mbytes x 6, 256 Mbytes x 1 |
|Data bus width : External 8/16/32 bits |
|On-chip peripheral functions ||16-bit timer (MTU2) x 6 channels |
|8-bit timer (TMR) x 2 channels |
|A/D converter (10-bit resolution) x 8 channels |
|D/A converter (8-bit resolution) x 2 channels |
|Serial communication interface with 16-stage FIFO (SCIF) x 8 channels (asynchronous and synchronous communication capability) |
|I 2 C bus interface x 3 channels |
|Serial sound interface (SSI) x 2 channels |
|CAN controller (RCAN-ET) x 2 channels ||- |
|- ||IEBus controller x 1 channel |
|CD-ROM decoder |
|Real-time clock (RTC) |
|User break controller (UBC) |
|On-chip debugging functions • Advanced user debugger-II (AUD-II) • User debug interface (H-UDI) |
|Direct memory access controller (DMAC) x 8 channels |
|Interrupt controller (INTC) |
|Watchdog timer (WDT) |
|Clock pulse generator (CPG) : Built-in PLL, max. 16 x multiplication |
|Power-down modes ||Sleep mode |
|Software standby mode |
|Deep standby mode |
|Module standby mode |
|Package ||176-pin LQFP (24 mm x 24 mm) |