ASIC Architect Announces Immediate Availability of Soft IP for 4-Port Configurable Switch for PCI Express

SANTA CLARA, CA., August 23, 2005 -- ASIC Architect, Inc., a leading provider of Cores and Solutions for PCI Express, today announced that the company has released a highly scalable, low silicon footprint soft IP for a 4-port switch for PCI Express. The customers of ASIC Architect’s Switch Core can leverage this soft IP for 4-port switch in designing their complete Switch ASIC for PCI Express.

“ASIC Architect specializes in PCI Express Technology. The company is committed to bringing the best-in-class products and solutions to the customers in the domain of PCI Express. This soft IP for 4-port configurable switch is an important addition to our existing soft IP solutions for PCI Express,” said Kishore Mishra, President and CEO of ASIC Architect. “The architecture is the most critical part of a good solution, and is key to time to market and success of the end product. In designing of the 4-port switch soft IP for PCI Express, we have followed an innovative architecture that is scalable, configurable, testable, and our end customers will directly benefit in the form of low silicon footprint and high performance.”

Key Features:

• One upstream port to interface with the Root Port.
• Upto Three downstream ports to interface with Endpoint Ports.
• Supports Two Virtual Channels
• Configurable Lane Width – x8, x4, x2, x1
• Peer-to-Peer Communication Support
• Non-blocking Routing Architecture
• Complete Power Management Support

About ASIC Architect Products
ASIC Architect offers a wide range of Cores for PCI Express – Endpoint, Dual Mode – Root and Endpoint, Root Port, Switch Port and related Solution Cores for ASIC and FPGA. ASIC Architect is included in PCI-SIG Integrators List. For a more detailed datasheet, click here

Key Features:

• PCI Express Specification 1.1 Compliant
• Low Silicon Footprint
• Low Tx/Rx/Ack Latency
• Choice of 8-bit or 16-bit PIPE Mode
• Supports x16, x8, x4, x2, x1 Lanes.
• Choice of 32/64/128 bit Datapath on Application Interface
• Technology Independent Design for ASIC, FPGA
• Excellent Support from Core Integration through Silicon Bring-up

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