Tensilica'’s Synthesizable Xtensa V Processor Core Reaches 500 MHz Clock Rate in STMicroelectronics 90 nm Fab

Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)

Xtensa LX processor simulated at 700 MHz

Geneva and Santa Clara, Calif. – August 29, 2005 – Tensilica®, Inc. today announced that STMicroelectronics (NYSE:STM) has achieved first silicon success on a chip that proves Tensilica’s Xtensa® V configurable processor achieves a clock rate of 500 MHz in a 90nm process technology. ST’s simulations on a second design expected to go into fabrication in a couple of months, using Tensilica’s Xtensa LX processor, shows that Xtensa LX reaches 700 MHz in 90nm technology, which makes it the industry’s fastest synthesizable, configurable core.

ST configured the Xtensa V processor to typical networking multi-processor applications and optimized its implementation onto the target 90nm technology, with dedicated 32k-byte cache design and advanced physical synthesis techniques. The resulting silicon achieved 500MHz operations at 0.9V, while keeping a very low power profile of 0.16 mW/MHz.

These results make the Xtensa LX and Xtensa V processors attractive, both for traditional CPU control applications, and for high-speed application acceleration like alternatives to hard-coded RTL (register-transfer-level) block designs. Besides being fully programmable 32-bit processors, the Xtensa configurable processors are much faster to design and are automatically verified and guaranteed correct by construction. Designers can run their existing C/C++ algorithms through Tensilica’s XPRES™ Compiler to automatically customize the Xtensa LX processor in less than an hour, whereas a typical RTL design cycle usually requires six to nine months of design effort.

Tensilica worked closely with ST on this pilot project to evaluate the speed and ease of designing with Xtensa processors. “We really appreciate the effort of ST to prove that the Xtensa LX processor is the fastest synthesizable, configurable core. Our mutual customers can be assured they will get the high performance they need in their designs by using ST’s 90nm design platform,” stated Chris Rowen, president and CEO of Tensilica. “Those design teams that have the most demanding clock rate requirements should take a serious look at the ST high-performance 90nm process.”

ST’s 90nm design platform is intended for System-on-Chip (SoC) and ASIC solutions that target wireless, consumer and networking applications. It features as many as 9 metal layers of copper interconnect, low-k dielectric, dual-gate oxide, and dual-Vt transistors. Standard cell libraries containing more than 1000 cells feature 11ps gate delay and a library density of more than 400,000 gates per mm2.

“Many of our ASIC customers are looking at Tensilica’s Xtensa processors as a way to add extra flexibility to their designs, especially as they make the investment in 90 nm technology,” stated Flavio Benetti, WLI Division ASIC BU Director, STMicroelectronics. “The high clock rates possible with these processors make them an attractive alternative to RTL design, particularly because they can be modified to match the particular application so quickly.”

About Tensilica

Tensilica was founded in July 1997 to address the growing need for optimized, application-specific microprocessor solutions in high-volume embedded applications. With a configurable and extensible microprocessor core called Xtensa, Tensilica is the only company that has automated and patented the time-consuming process of generating a customized microprocessor core along with a complete software development tool environment, producing new configurations in a matter of hours. For more information, visit www.tensilica.com.

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