Chipidea's 0.13µm Low Power I&Q ADC designed for DVB-H/DMB systems excels in Silicon
Update: MIPS Technologies Acquires Chipidea (August 27, 2007)
September 5, 2005 -- CHIPIDEA´s 0.13µm Low Power I&Q ADC designed for DVB-H/DMB systems excels in Silicon CHIPIDEA´s 0.13µm Low Power 10-bit I&QADC was designed for Handheld Digital TV receivers supporting the emerging DVB-H video standard. This is an excellent Analog-to-Digital interface for receivers in portable systems, such as PDAs, phones, and PMPs. The CI3611ul is successfully embedded in an application specific SoC.Brief Description
- 0.13 µm CMOS, 1P6M, no analog options
- IQ Matched ADC Pair
- 10-bit Resolution
- 1 MHz to 50 MHz Sampling Rate
- S/H stage for wide input common mode range
- 1.2V ±10% Analog and Digital Supply
- 2.5 V to 3.6V Analog Power Supply for the input interface
- Power Dissipation: 12mW @ 8.2Msps
- Power Dissipation: 31mW @ 30Msps
- Flexible power-down modes
- Core Cell Area: 1.0 mm2
The following block diagram illustrates the CI3611ul:
It is composed of a dual fully differential high speed low-power pipelined ADC core suitable for receive channels in I&Q configuration.
Dedicated S/H circuits are built-in to provide direct DC coupling with common mode voltage from 0.5V to 2V, and offering an optional single-ended to fully differential conversion.
The reference voltages are internally generated from an internal bandgap reference, with outside connection for decoupling purposes.
A power down capability is included for extremely low power dissipation in stand-by mode.
... and outstanding linearity:
For SoC integration, Chipidea offers a wide range of Analog-Digital Interface Systems for Audio, Video, Multimedia, Data-Communications and Connectivity, including Power and Clock Management functions.
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