| BANGALORE, India With efficient test access architecture of much interest to the SoC design and test community, two researchers at an Indian technical institute have proposed a design-for-test method for digital SoC designs using a Test Access Mechanism (TAM) switch. |
Shibaji Banerjee and Dipanwita Roy Chowdhury of the Indian Institute of Technology, Kharagpur, have developed a new test strategy algorithm to exploit the possible parallelism of testing the cores. The algorithm generates the needed TAM switches, the configuration information of all the TAM switches and also TAM-to-Core connection need for the SoC under test.
A new computer aided test (CAT) tool has also been developed to test the SoC designs, they said.
In a sequential core, only scan chains are considered for testing as flip flops are more defect prone, so no extra hardware except the TAM switch is needed for the test. The benefit of considering only scan chains is that they can be tested in parallel. The test access mechanism is implemented on-chip by using a special TAM switch, and a synthesizable RTL core can be instantiated in a design to provide test access data to embedded cores in the SoC.
The TAM switch is a programmable cross bar switch allowing efficient delivery of test vectors to embedded cores at varying bandwidth. It has two useful operational modes-- in the cross configuration the switch is configured to send the test patterns to the core-under-test. while in the pass configuration the switch passes the test patterns to the next switch.
The proposed scheduling algorithm is divided into that for sequential cores in the SoC, another for combinational cores in the SoC and a third for the SoC with both sequential and combinational cores. During scheduling, the higher priority nodes are scheduled first, based on lower label nodes having higher priority than those with higher labels, while among nodes having the same label nodes with higher weight get priority.
The proposed scheduling algorithm has been implemented and experimented on the ITC ’02 SoC test benchmark; the experiments were done on Sun Sparc Ultra 60 workstation in Solaris 5.8. The new CAT tool has been demonstrated for the ITC ’02 test benchmarks. The experiments showed significant reduction of the time taken for system-level testing, the researchers said.