Lowest Cost per Channel of Any ADPCM Core, Cuts FPGA Silicon Cost By 72%
OCTOBER 23, 2000, IP 2000, EDINBURGH, SCOTLAND - Frontier Design today announced the immediate availability of four adaptive differential pulse code modulation (ADPCM) intellectual property cores. Both single and multi-channel cores are available in either VHDL (IEEE1076-1987) or Verilog (IEEE 1364-1993) for optimized implementation in Xilinx VirtexTM XCV400E, XCV200E or XCV150 FPGAs, as well as for standard cell-based ASIC implementations. Frontier Design’s ADPCM core is also available in a bit-true C-language implementation that can be parameterized for different applications.
ADPCM is rapidly gaining acceptance as the standard for Voice-over Internet Protocol (VoIP) for Internet-based voice transmission, digital telephony, intercoms, telephone answering machines, and mass storage. It leverages legacy equipment by allowing the integration of corporate PABX systems with digital LANs and WANs. Since telephone transmissions over the Internet are free of charge, VoIP systems can offer substantial savings on telephone charges. On average, corporate VoIP users cut 40% from their usual telephone bill.
According to Herman Beke, Frontier Design’s CEO, "VoIP traffic is expected to more than double every year between now and 2004, when it is expected to reach 135 billion minutes per year. Low cost, high capacity system-on-a-chip solutions are required to support this phenomenal growth. We believe that our ADPCM IP core will be the basis for much of this growth because it offers the lowest silicon cost of implementation, as well as the lowest IP cost per ADPCM channel.
"This highly efficient, highly parallelized core would not have been possible without Frontier Design’s A|RTTM Builder C-to-HDL translation tool. Our IP design team used A|RT Builder to generate the single cycle implementation of the ADPCM core. A few adjustments were made to the algorithm to improve its efficiency, but A|RT Builder automatically generated the core, which is the only single-cycle ADPCM core on the market." Beke concluded.
Like other ADPCM cores, the Frontier core is fully programmable for 16, 24, 32, or 40-bit kbps operation, with programmable A-law, u-law or linear coding of input or output. Both cores are fully compliant with ITU recommended G.726 test vectors.
Highest Capacity ADPCM Core Available for Virtex FPGAs - Frontier Design’s highly parallelized core executes the ADPCM algorithm in a single clock cycle, allowing it to handle 256 ADPCM channels in a single XCV200E device, or 128 channels in the less costly XCV150. The core has a 2.048 MHz clock in both devices, for low power operation. The capacity of the Frontier Design core is eight times greater than that offered by the company’s nearest competitor, ISS, which only offers 64 channels (32 duplex channels) in the same XCV200E FPGA. The ISS core also requires a 21.3 MHz clock and, therefore, consumes ten times more power. Frontier Design’s core can handle 512 channels in an XCV400E Virtex, operating at 4.096 MHz.
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Frontier’s unique implementation of the ADPCM algorithm provides the single cycle execution that allows the high number of channels to be implemented in a single Virtex device. The 512 channel Virtex implementation requires 2,306 slices and 36 block RAMs. The 256 channel Virtex implementation requires 2,020 slices and 18 Block RAMs. The 128 channel Virtex implementation requires 1,800 slices, but only 9 Block RAMs.
Lowest Cost ADPCM FPGA Implementation Available - The high number of channels in Frontier’s core allows telephone and VoIP servers to be implemented in many fewer FPGAs than with competing IP cores, resulting in substantial cost savings. For example, the DS3 lines provided by phone companies for dedicated, point-to-point communications each support 672 voice channels. Using the Frontier core, all 672 channels can be handled in just three Xilinx XCV200E devices. In comparison, The ISS ADPCM core, marketed by Xilinx, has only 64 channels and requires eleven XCV200E Virtexes, or nearly four times as many devices to handle all 672 channels. At a price of $30 to $70 per FPGA, the device cost of implementing ADPCM for a single DS3 line would be between $330 and $770 per line, using the ISS core, but only $90 to $210 using the Frontier core.
ASIC Implementation Offers as Many as 6,250 Channels -. Frontier Design’s ADPCM core needs a clock frequency of just 8 kHz per channel, so 128 channels can be encoded or decoded with a 1.024 MHz clock. Each channel of ADPCM encoding and decoding requires 280 bits of dual-port memory. The ASIC implementation of the Frontier’s 256 channel core requires about 20,000 gates or 78 gates per channel, operating at 2.048 MHz Using a 0.18 micron process, a clock speed of about 12.5 MHz is attainable, allowing 1,562 channels to be implemented in the 20,000 gate core. Thus, all 672 channels required for two DS3 lines can be easily implemented in 20,000 ASIC gates. With additional pipelining Frontier’s ADPCM ASIC core can handle as many as 6,250 channels, allowing seven DS3 lines to be encoded/decoded in a the core. Four additional pipeline stages would increase the gate count to 32,000. No other ADPCM core can boast this level of performance or silicon efficiency.
In contrast, with its maximum clock of 2 MHz, Mentor’s InventraTM multi-channel ADPCM ASIC core can handle a maximum of only16 channels in 20,000 gates -- about 6% as many channels as Frontier’s non-pipelined core. In addition, each of Frontier Design’s encoding or decoding channels needs just a single clock cycle per sample, compared to 16 cycles for the Inventra core.
Ultra Low Power Single Channel Core - Frontier Design’s single channel ADPCM ASIC and FPGA cores require a clock of only 8 kHz, so power consumption is minuscule, making these cores ideal in portable applications such as mobile telephones and Internet appliances.
Frontier Design’s ADPCM ASIC and FPGA cores are available in both Verilog and VHDL.
Fully-programmable - Each channel of ADPCM encoding or decoding can be configured separately using a 6-bit wide mode-control word. Bits 5 and 4 determine the input/output encoding and each channel can be individually configured for linear, A-law or u-law encoding. Bits 3 and 2 determine the ADPCM speed of 40 kbps, 32 kbps. 24 kbps or16 kbps for each channel. Bit 1 determines whether a channel is used for encoding or decoding and bit 0 is used to initialize each channel. Initialization is performed outside the RAM memory without adding extra clock cycles.
Output latency is two cycles, so the output is available two cycles after the encoding is started. Custom configurations (e.g. with single- port memory) are also available. For example, if only a
32-bit wide memory is available, then the core can be configured to use nine cycles to read and write the state of the ADPCM core to or from memory.
Availability, Pricing and Support - Altogether, Frontier Design offers four ADPCM IP cores. These include single channel and multichannel ADPCM cores for cell-based ASICs and single and multichannel ADPCM cores for Virtex FPGAs. All four cores are available in VHDL or Verilog source code and include a bit-true C-language compiled executable for verification, HDL test bench stimuli and reference vectors, Synopsys Design Compiler and Exemplar Leonardo synthesis scripts, plus one week of technical support. The licensing fees for first time use, including test benches and technical support, are as follows:
| ADPCM Core | Maximum Channels | Clock | | Cost per Channel |
| Single Channel ASIC | 1 | 8 kHz | $25,000 | $25,000 |
| Multichannel ASIC | 1,562 | 12.5 MHz | $40,000 | $ 26 |
| Single Channel Virtex | 1 | 8 kHz | $20,000 | $20,000 |
| Multichannel Virtex (XCV200E) | 256 | 2 MHz | $25,000 | $ 98 |
For a higher price the cores may be purchased outright. Substantial discounts of up to 80% are available for second and subsequent licenses of Frontier Design’s ADPCM core.
Frontier Design’s per channel pricing of the multichannel Virtex core is less than 1/2 the $227 cost per channel of the 64-channel ISS core. With its maximum clock of 12.5 MHz, the per channel cost of the multichannel ASIC version is only $26, 96% less than the per channel cost of the Inventra core*. Custom implementations are also available from Frontier Design’s Design Service Group.
A comparison of the costs and capacity of competitive ADPCM core is shown below.
Comparison of Selected Virtex (XCV200E) Multi-channel ADPCM Cores
| | | | Channel | | |
| Frontier Design | | | | | 2.048 |
| ISS | | | | | 21.300 |
Comparison of Selected ASIC Multi-channel ADPCM Cores
| | | | Channel | | |
| Frontier Design | | $ 26 | | 13 | 12.500 |
| Mentor Graphics | | $ 625* | | 1,250 | 2.00 |
Frontier Design’s World Wide Web site is http://www.frontierd.com. Email inquiries may be sent to info@frontierd.com.
* Assumes $10,000 price for Inventra core.
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Frontier Design was founded in 1997 as the result of a management buy-out of the European Development Center of Mentor Graphics (NASDAQ: MENT). The firm’s primary emphasis is its "algorithm-to-silicon" design methodology that greatly improves the creation of Silicon IP blocks starting from customer- proprietary or industry-standard algorithms in the fields of wireless telecom, consumer audio or multimedia applications. Algorithm-to-Silicon IP blocks consume less power, are less costly and require substantially less development time than other alternatives. Frontier Design sells its design services and a line of EDA tools directly from its facility in Leuven, Belgium, and from its sales office in California. Frontier Design also sells through a growing number of distributors and Value Added Resellers in Northern America, Europe, Japan and the Pacific Rim.
A|RT is a trademark of Frontier Design. Virtex is a trademark of Xilinx Corporation. Inventra is a trademark of Mentor Graphics Corporation.
Contacts:
Herman Beke
Frontier Design
+32 16 39 14 11
herman_beke@frontierd.comNancy B. Green
The William Baldwin Group
+1 650 856 6192
nancybgreen@william-baldwin.com