MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm) for Automotive
Micro Digital Announces GoFast for Nios II
Costa Mesa, California, September 15, 2005 - Micro Digital Inc. is pleased to announce that the GoFast floating point library has been ported to the Altera® Corporation's Nios II embedded processor family.
GoFast is a family of high-performance, reentrant, floating-point libraries designed for embedded applications. They are ANSI C compatible and are designed to directly replace a C compiler's runtime floating-point support (library or coprocessor). GoFast boosts the performance of an application's math calculations or eliminates the need for hardware floating-point coprocessors, in order to reduce product manufacturing cost.
By using the GoFast library, developers can achieve a significant performance boost in their Nios II floating-point operations. Peformance increases vary from 3:1 for most arithmetic operations, such as addition, up to 10:1 for more advanced operations, such as arctangent.
"The GoFast floating point libraries provide our Nios II system of designers with increased design flexibility while meeting their system performance goals," said Chris Balough, Altera's director of software and Nios marketing. "System designers can quickley realize substantial performance gains in their math intensive software algorithms, while preserving their valuable FPGA resources for other functions."
Pricing and Availability
Available now at $2,500 for a royalty free, one-product license, with full source code, and 90 day support. For more information, please visit www.smxrtos.com/gfnios.htm.
About Micro Digital
Micro Digital, Inc. has been in the embedded systems business for over 30 years and has been producing and selling embedded products for 16 years. The company is dedicated to providing quality products and support for embedded systems at moderate prices.
|
Related News
- Digital Blocks Announces I2C-Master Controller IP Core Family with the availability of the DB-I2C-M for the ARM AMBA 2.0 APB and Altera NIOS II Avalon Interconnects
- Morse Micro Raises $140M in Series B Funding to Accelerate IoT Connectivity and Revolutionize our Digital Future
- Altera Functional Safety Package Combines FPGA Flexibility with "Lockstep" Processor Solution to Reduce Risk and Time-to-Market
- Altera Nios II Processor Model Delivered By Imperas
- Altera's DO-254/ED-80 Certifiable Nios II Processor Leveraged in Thales Safety-Critical Avionics System Certified by EASA
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- SEMIFIVE Starts Mass Production of its 14nm AI Inference SoC Platform based Product
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
Most Popular
- Qualitas Semiconductor and Ambarella Sign Licensing Agreement
- ZeroPoint Technologies Signs Global Customer to Bring Hardware-Accelerated Compression to Hyperscale Data Centers
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- Intel and Arm Team Up to Power Startups
- Alphawave Semi and InnoLight Collaborate to Demonstrate Low Latency Linear Pluggable Optics with PCIe 6.0® Subsystem Solution for High-Performance AI Infrastructure at OFC 2024
E-mail This Article | Printer-Friendly Page |