UMC sees SoC driving 90 nm's growth

Taipei, Taiwan — By the end of this quarter, foundry United Microelectronics Corp. predicts, 90-nanometer technology will account for about 15 percent of its revenue. And by year's end, UMC's monthly wafer shipments will double from the 10,000 or so it was hitting during the summer.

So all is well in 90-nm land, right? Perhaps for UMC, which established an early lead in the 90-nm ramp-up over rival Taiwan Semiconductor Manufacturing Co. — although the latter still derives nearly double the revenue from advanced technologies. TSMC believes that it will derive 10 percent of fourth-quarter sales from 90 nm, up from about 2 percent in the second quarter. One report said those sales could triple next year.

At UMC, the ramp of 90 nm has been steady, but not eye-popping — just a little ahead of the pace of its 130-nm ramp-up. Still, UMC has shipped more than 100,000 wafers using 90-nm technology, and believes the growing popularity of system-on-chip products will accelerate the uptake beyond that of 130 nm. "The trend toward SoC is real," said Lee Chung, vice president of corporate marketing at UMC. "The feature-rich handsets and multimedia electronic devices so commonplace today are all SoC-enabled."

The foundry is seeing a variety of applications move into 90 nm, covering all three market segments: communications, computing and consumer. UMC argues that 90 nm is mature technology, with pilot production beginning in 2003, and further believes that there are no major technology hurdles that should prevent designers from adopting it.

"The 130-nm generation introduced new materials such as copper and low-k, which introduced a new learning curve. Since 90 nm uses the same materials, no such issue exists, making migration to 90 nm much more seamless," Chung said. He added that low-k dielectrics are quite mature today because of more than four years of manufacturing experience.

Cost questions
Nevertheless, many designers remain reluctant — for many of the reasons that caused a double-take during the transition to 130-nm technology. Kalar Rajendiran, senior director of marketing at eSilicon Corp. (Sunnyvale, Calif.), said the stories of huge mask and development costs at 90 nm remain an emotional barrier to many design teams. This has broken the tradition of automatic migration to the newest process with each succeeding chip design.

Instead, design teams look more closely at whether — and why — they should migrate. "There are two kinds of designs that see benefits to 90 nm now," Rajendiran said. "On one hand, there are consumer designs that have relatively mild performance requirements and quite small dice. These people can do a conservative design, get a very small die size and hence many more dice per wafer. Those economies of scale from 300-mm wafers — if the foundry chooses to pass them along — mean excellent cost."

The other category is at the opposite end: the 15-mm-on-a-side dice in high-end networking and other system-on-chip applications. "Here, the die shrink at 90 nm means lower chip area, and so lower defect-related yield loss," Rajendiran said.

But for designs in the middle, with dice 8 mm or 10 mm on a side, "these guys are kind of stuck," Rajendiran said. "The foundries really haven't articulated benefits that would apply to this group."

Designs in this category may not see a significant yield or cost advantage, and face the high mask costs, complex design rules and chance of pattern-dependent yield problems. "We keep waiting for the foundries to give us a set of rules that will guarantee no pattern-dependent defects on 90-nm designs," Rajendiran said. "We haven't seen one yet."

Notably absent from the list of reasons to migrate is performance. "The performance gain at 90 nm can be there," Rajendiran said, "but only if you can handle a huge increase in leakage current. Most design teams in search of higher performance now are staying at 130 nm and looking for architectural or other ways to make the system go faster."

Intellectual-property (IP) providers are weighing in with respins of their libraries as one way of putting off the migration. In the next couple of weeks, design services and IP outfit Faraday Technology Corp. (Hsinchu, Taiwan) will release a "mini-IP" library for 130 nm. It will be a follow-on to its respin of 180-nm IP released last month. Faraday believes that even with all the hype, 130-nm technology still isn't a viable option for many cost-sensitive consumer devices, due to the high mask cost, long turnaround time and high design risks, said Hsin-shih Wang, associate vice president of Faraday.

With mask costs jumping to $750,000 at 130 nm, and more than $1 million at 90 nm, Wang said, many small to medium-size IC design houses are still opting to squeeze their designs for more efficiency rather than undertake the migration.

For big companies
Faraday's mini-IP platform seems to do just that. It includes the miniLib, which is a high-density cell library of 145 kgates/

mm2 that is said to offer a 20 percent to 30 percent reduction in core logic area and power consumption when compared with other standard-cell libraries. MiniLib is suitable for devices operating at 1.35 to 1.98 volts, the company said.

Wang said he has had several inquiries from IP customers about 90 nm, mostly for applications with high volumes, like MP3 players and wireless products. But only 1 or 2 percent of Faraday's ASIC design customers are interested. "Huge, consumer companies want 90 nm, but not small companies," he said. "Performance is one of the biggest reasons

for small companies to jump into 0.13 [micron] — maybe their CPU can do 500 MHz at 0.13 but not 0.18. If they want the CPU to work at 800 MHz or 1 GHz, they will probably need to go to 90 nm."

"We've seen a lot of designers looking at 90 nm with lofty power and performance goals, and then backing off," said James Lee, president of The ASIC Group. "They tend to go away and come back with a better idea for the design that has less-stringent requirements.

"It's often possible to meet your system requirements by being clever, rather than by demanding a faster or lower-power process node," Lee said. "For example, one design team I know of in the medical area is meeting some substantial performance goals in 0.35-micron CMOS, where the leakage is extremely low and they can manage the active power very well."

Lee said that cost was very much an issue. "There is a huge cost difference between a 180-nm and a 90-nm design," he said. And there exists what he called an undercurrent of concern about design risk at 90 nm. Noise margins are much thinner, and the list of additional physical-verification steps necessary at 90 nm is long.

"There is a huge amount of additional analysis involved in a 90-nm design," Lee warned. "At a minimum, I'd want to be sure that my back-end team was up to speed on all the new challenges."

Another indicator that designers may wait and see came recently from equipment maker Applied Materials, which normally sells 30 percent of its orders to foundries. That level is now hovering around 10 percent. Since virtually all of Applied's business is for leading-edge 300-mm equipment, that would suggest the foundries don't plan to increase advanced capacity anytime soon.