ESL Software Generates Soft-IP From XML-Based SpecificationsVANCOUVER, BC--Sep 26, 2005
-- Productivity Design Tools (PDTi), a new EDA company, today announced that it is developing electronic system level (ESL) software that manages specifications, enabling system-on-a-chip (SoC) developers to automate all aspects of code and documentation generation. PDTi provides chip developers with an extensible tool-based methodology that enables project-wide synchronization, automated re-engineering, and improved opportunities for reuse. The privately funded Company is focused on achieving efficiency improvements in chip development through better abstraction and reuse.
PDTi's first product, SpectaReg, is a soft-IP Generator for memory-mapped registers. SpectaReg automates code and documentation generation for registers, which chip developers commonly use for interfacing hardware and software. Register-maps are an aspect of IP design that is very tedious to develop, yet fundamental in creating more configurable chips that are applicable to a wider-range of applications. SpectaReg is built on PDTi's SpectaGen Framework(TM) -- a powerful methodology and tool infrastructure for building generic and reusable families of IP components. More details regarding the product, which is aimed at the new Target Compiler market category, will be released at a later date.
In a recent EETimes article (August 8, 2005) discussing Denali's Blueprint product that targets a similar design task, Gary Smith, chief EDA analyst at Gartner Dataquest, indicated that such compilers are a "natural fit" to complement IP blocks. In the article Smith also notes that, "Too many EDA companies are standing still right now." Dataquest's Daya Nadamuni echoes Smith's endorsement of ESL tools. When asked in a June 13, 2005 EETimes article about what will drive EDA growth, Nadamuni stated that, "It really seems like ESL is going to be the savior."
"Using tools based on our SpectaGen Framework, hardware, software, verification, validation and documentation teams can automate their work from a common 'golden' specification," said Jeremy Ralph, president and chief executive officer at Productivity Design Tools. "We are excited to introduce our new product to the market. PDTi is currently seeking beta customers to help with further development of our memory-mapped register tool."
Through PDTi's ongoing interaction with chip-development experts and prospective customers, the Company has established that there is a strong need for the types of tools it is developing. In many cases, chip developers have put together ad-hoc in-house solutions to address immediate needs. PDTi anticipates increasing need for such tools as electronics systems continue to become more complex and times-to-market continue to shrink for SoCs.
PDTi acknowledges that there are some companies working on competing products, but believes its biggest competition comes from prospective customers who have in-house generator tools. Almost all the EDA companies in this marketspace are competing simultaneously in adjacent markets, which consume substantial portions of their resources. Meanwhile, developers of in-house tools often allocate an unreasonably small budget for tool development, resulting in shaky solutions that don't scale well across projects. The support and maintenance of these in-house tools is often overlooked and under-resourced. PDTi believes it is demonstrably cheaper and less risky for companies to buy tools and focus on doing what they do best -- design chips.
PDTi's inaugural product utilizes the industry-standard Structure for Packaging Integrating and Reusing Intellectual Property within Tool-flows (SPIRIT), which is being developed by the SPIRIT Consortium to raise the level of automation and to cut costs in developing SoCs from modular IP blocks. As a reviewing member of the SPIRIT Consortium, PDTi looks forward to deploying tools to enable customer benefit from adoption of the standard.
"The SPIRIT standard is being developed as an enabler for an ecosystem addressing the wide field of SoC development from high-level abstraction through RTL, verification and design tool flow," said Ralph von Vignau, Chair of the SPIRIT Consortium. "Such concepts as reuse, interoperability and ease of integration open many opportunities for innovative concepts. The SPIRIT Consortium welcomes the SpectaReg tool being developed by Productivity Design Tools, based on the SPIRIT 1.1 standard, as another important component in the growing SPIRIT ecosystem."
PDTi is providing a solution that is flexible enough for any environment, enabling engineers to extend tool-offerings based on their specific knowledge and design experience. This simplifies integration with or replacement of in-house solutions. PDTi's SpectaGen Framework(TM) enables engineers to extend the scope of captured IP specifications, object-oriented modeling, and the look and feel of generated code and documentation using a Python-based programming interface. Python is an open and well established Very High Level Language (VHLL) that is naturally suited for high-level tasks such as IP modeling and code and documentation generation (www.python.org
).About Productivity Design Tools SpectaGen Framework(TM)
The SpectaGen Framework(TM) is a powerful methodology and tool infrastructure for building generic and reusable families of IP components. The framework enables the creation of extensible domain-specific IP generators that capture specifications in a machine-readable format, enabling engineers to automate the tedious and repetitive process of manually converting specifications into code and documentation. SpectaGen applies proven XML and object-oriented techniques to the front-end of chip development, bridging the gap between specifications and implementation. This maintains synchronization between changing specifications and dependent code and documentation, reducing re-engineering efforts and improving opportunities for reusing IP.About Productivity Design Tools
Productivity Design Tools is an EDA company providing the most flexible system-level tools for managing IP specifications, and automating code and documentation generation for all aspects of chip development. The company was founded by Jeremy Ralph, a former ASIC and firmware engineer. Utilizing its SpectaGen Framework(TM), Productivity Design Tools builds extensible Soft-IP Generators that output hardware, software, verification and validation code, and documentation in industry-standard formats. By bridging the gap between 'golden' specifications, and dependent code and documentation views, Productivity Design Tools enables project-wide synchronization, reducing tedious work, automating re-engineering, and improving opportunities for IP reuse. Productivity Design Tools' corporate headquarters are located in Vancouver, BC, Canada. For more information, visit Productivity Design Tools at www.productive-eda.com
, call (604) 739-8534.