Test Chip, Libraries, Technology Files and RTL-to-GDSII Reference Flow Demonstrate Predictable Path to Silicon Success with Shortened Time to Market
HSINCHU, Taiwan-Sept. 27, 2005-UMC (NYSE:UMC), a leading semiconductor foundry, today introduced the industry's most comprehensive low-power reference design package to specifically target the needs of low power, system-on-chip (SoC) designers. The offering delivers a fast, more predictable path to silicon success and sets a new precedent in the foundry industry in terms of providing customers with a complete solution to help shorten their product development time for low power designs. This technology enabler for nanometer designs is available for UMC's 0.13um process today, and includes:
- Silicon-verified test chip that features the open-source LEON2 SPARC processor
- Process optimized low-power libraries
- Low power technology files
- Integrated RTL-to-GDSII reference flow incorporating the latest tools from Cadence Design Systems Inc. (NYSE: CDN) (NASDAQ: CDN) and Mentor Graphics (NASDAQ: MENT)
"As designs scale to smaller process technologies, leakage and other power challenges become bigger obstacles for SoC designers," said Ken Liou, director of the IP and Design Support division at UMC. "To effectively address these issues, designers need a total package solution that will help guide them efficiently through the design process. With the delivery of this comprehensive offering, we are providing designers with key resources to help them quickly and successfully bring their low-power ICs to market."
The reference design package expands well beyond a typical foundry reference flow to also include a host of other silicon-verified resources developed to work together. Low power SoC developers can reference the test chip that includes a LEON2 processor-the open source synthesizable VHDL model of a 32-bit processor, while designing their own SoC designs. The chip design is highly configurable and expandable, allowing customers to plug in additional digital and/or analog/mixed signal (AMS) hard IP blocks, making it ideal for specific derivative designs that customers are evaluating. The chip can also be used for greater insight into the process or device side effects of advanced technology and to figure out solutions, set up a library and IP QA methodology through chip implementation, and validate process, library, IP, and EDA tools and flow before adoption.
The silicon-validated reference flow adopts the Cadence Encounter digital IC design platform, which includes Encounter RTL Compiler synthesis, SoC Encounter Global Physical Synthesis (GPS), VoltageStorm static and dynamic power analysis, and CeltIC Nanometer Delay Calculator (NDC). For design-for-test (DFT), it adopts the latest Mentor flow, which integrates MBISTArchitect, DFTAdvisor and TestKompress and for physical verification uses Mentor's Calibre tool. The reference flow provides the user with an understanding of the low-power design flow and in-depth DFT using the LEON2 based test chip as a reference design.
Silicon-proven libraries and technology files complete the low-power reference design package, and provide the basic building blocks for customers to begin their low-power SoC development. Customers interested in this offering should contact their UMC sales representative. About UMC
UMC (NYSE: UMC, TSE: 2303) is a leading global semiconductor foundry that manufactures advanced process ICs for applications spanning every major sector of the semiconductor industry. UMC delivers cutting-edge foundry technologies that enable sophisticated system-on-chip (SoC) designs, including 90nm copper, 0.13um copper, and mixed signal/RFCMOS. UMC is also a leader in 300mm manufacturing; Fab 12A in Taiwan and Singapore-based Fab 12i are both in volume production for a variety of customer products. UMC employs approximately 10,500 people worldwide and has offices in Taiwan, Japan, Singapore, Europe, and the United States. UMC can be found on the web at http://www.umc.com