Software Offers Graph-based Physical Synthesis and Simulator-like Visibility into FPGAs for Debug SUNNYVALE, Calif., October 3, 2005
— Synplicity® , Inc. (Nasdaq: SYNP), a leading supplier of software for the design and verification of semiconductors, today announced it has expanded its Synplify family of FPGA synthesis tools to address the design challenges presented by today’s complex FPGA devices. Synplicity’s Synplify® Premier software offers FPGA designers an integrated environment that features Synplicity’s industry-leading FPGA synthesis technology, a push-button physical synthesis flow utilizing its proprietary graph-based physical synthesis technology and powerful RTL debug based upon its popular Identify® RTL Debugger product. With the Synplify Premier software, Synplicity continues its commitment to delivering new innovative technologies for designing the latest generation of programmable logic devices.
The backbone of the Synplify Premier software is Synplicity’s new graph-based physical synthesis technology, an automated, single-pass design flow that delivers superior timing performance, dramatically improved timing correlation, and reduced design cycle time and iterations. Using this graph-based approach to physical synthesis, designers are able to close on aggressive timing requirements much faster while achieving a performance improvement of up to 20 percent compared to logic synthesis alone.
“Synplicity was the first to deliver physical synthesis for FPGAs, and with our next-generation graph-based approach to physical synthesis, Synplicity continues its commitment to technology innovation,” said Andy Haines, sr. vice president of marketing at Synplicity. “Better timing closure and physical optimizations all hinge on highly accurate timing estimations before running place and route. We believe our new graph-based physical synthesis technology delivers the accuracy needed to reduce design iterations and meet aggressive performance goals quickly and reliably.”A Graph-Based Approach to Physical Synthesis
Synplicity’s new graph-based physical synthesis technology, featured in the Synplify Premier software, creates a detailed routing resource graph of pre-existing wires, switches and placement sites used for routing an FPGA. With this graph, optimization and placement are driven by wire delay and actual availability of resources, rather than by measuring distance alone. Graph-based physical synthesis merges optimization, placement and routing to ensure critical paths of a design use the fastest routing resources available. This push-button physical synthesis flow generates a fully placed and physically optimized netlist ready for input to the FPGA vendor’s routing tool.
In using the Synplify Premier software in a recent project, Bjorn Halfen, senior design engineer at Dolphin Interconnect Solutions, said of the software, “By using the graph-based physical synthesis technology in Synplify Premier we were able to reduce the delay in our complex Xilinx Virtex-II Pro design from 14ns to 8ns without any floorplanning.”
By taking a graph-based approach to physical synthesis, the Synplify Premier software is able to deliver highly accurate timing correlation between the estimated and final post place and route (P&R) results, providing faster timing closure and reducing the number of iterations between synthesis and P&R. Internal testing suggests that 90 percent of the timing predictions produced by Synplify Premier software are within 10 percent of final post P&R timing, and 70 percent are within 5 percent of final timing. The automated, push-button flow requires no additional expertise from the FPGA designer and does not require a floorplan or other physical constraints to be used.
The automated graph-based physical synthesis flow within the Synplify Premier software currently supports Xilinx Virtex™-4, Virtex-II Pro and Spartan™-3 FPGA devices. Steve Lass, director, software marketing at Xilinx said, “With the Synplify Premier software, Synplicity continues to deliver on its strategy of offering solutions that provide excellent quality of results and productivity advantages. We are pleased to recommend the Synplify Premier software to our customers that require fast timing closure in our FPGAs.”Simulator-Like Visibility Into a Live FPGA
In addition to industry-leading synthesis results, the Synplify Premier software also provides a rapid method of finding functional errors in FPGA designs by providing simulator-like visibility into operating FPGA hardware. Synplicity’s integrated debugging software allows designers to annotate signals and conditions they want to monitor directly in their RTL code. Nodes that may be used as breakpoints and watch points are displayed for easy menu-driven instrumentation, and then seamlessly run through synthesis and P&R to implement the FPGA. Once the FPGA has been programmed, the RTL debugger is run, allowing users to view actual signal values from a running FPGA directly in their RTL code and debug it, in-system, and at the target operating speed. The tool offers advanced triggering that helps pinpoint design problems that could take a simulator days or weeks to uncover.ASIC Prototyping with FPGAs
As ASIC designers increasingly depend upon FPGAs to prototype all or part of their designs, there is a need for a synthesis and verification environment that can take HDL code written for an ASIC and efficiently implement it in an FPGA. The Synplify Premier software accommodates this by performing gated-clock conversion and handling generated clocks and Synopsys DesignWare® components automatically. The Synplify Premier software addresses single FPGA prototypes, while Synplicity’s Certify® RTL prototyping product enables multiple FPGA prototypes with advanced partitioning and pin multiplexing technology.Pricing and Availability
The Synplify Premier software is available now. Pricing for the software starts at $34,000 (USD). For more information, visit Synplicity’s Web site at http://www.synplicity.com
Synplicity, Inc. (Nasdaq: SYNP) is a leading supplier of innovative synthesis, verification and physical implementation software solutions that enable the rapid and effective design and verification of semiconductors. Synplicity’s high-quality, high-performance tools significantly reduce costs and time-to-market for FPGA, Structured/Platform ASIC and cell-based/COT ASIC designers. The company’s underlying Behavior Extracting Synthesis Technology® (BEST ™), which is embedded in its logical, physical and verification tools, and has led to Synplicity’s top position in FPGA synthesis, now provides the same fast runtimes and quality of results to ASIC and COT customers. The company’s fast, easy-to-use products support industry standard design languages (VHDL and Verilog) and run on popular platforms. Synplicity employs over 290 people in its 20 facilities worldwide. Synplicity is headquartered in Sunnyvale, California. For more information visit http://www.synplicity.com