SECURITY: CPU ARMed for smaller enterprises
EE Times: SECURITY: CPU ARMed for smaller enterprises | |
Loring Wirbel (10/03/2005 9:00 AM EDT) URL: http://www.eetimes.com/showArticle.jhtml?articleID=171201686 | |
Colorado Springs, Colo. SafeNet Inc. has designed an ARM-based security processor specifically for the small- and midsize enterprise market, allowing the T1/T3 market to move to the same single-chip solution characterized at higher speeds. The 51xx family combines an on-chip 450-MHz ARMv4 processor with an in-line data path engine that performs flow classification, packet filtering and processing of such protocols as Network Address Translation and Internet Protocol Secure (IPsec), said Bill Anderson, marketing manager in SafeNet's embedded division.
The packet-forwarding engine, formerly a lookaside engine, has been reimplemented as a full in-line device with dedicated intellectual-property blocks for classification. Its speed has allowed SafeNet to implement three versions of the 51xx family: The 5140 supports bidirectional 45-Mbit/second T3 channels; the 5150 supports bidirectional Fast Ethernet; and the 5160 supports bidirectional 155-Mbit OC-3 lines.
The ARM core can handle higher-layer tasks like Transport Layer Security, so that Secure Sockets Layer (SSL) virtual private networks can be implemented with ARM, even as the in-line processor handles IPsec and other protocols. Anderson said the small and midsize business market is demanding very small systems that can simultaneously handle IPsec, firewall, bulk encryption and SSL VPN.
Interfaces for the processor include dual GMII, PCI-X, 32-bit DDR DRAM, 32-bit SRAM, I2C, GPIO and USB 2.0 On-the-Go.
The three processors are sampling now. SafeNet is also offering evaluation boards, and its QuickSec Unified software as a preintegrated option with chip sets to provide multilayer security applications.
| |
- - | |
Related News
- Digital Core Design Presents DAES XTS Cryptographic CPU for Unparalleled Security
- Andes Technology Corporation Announces Most Advanced Embedded Security Based on Physical Unclonable Functions From Intrinsic-ID Inc. for Its Secure CPU/MCU Cores
- Renesas Introduces Industry's First General-Purpose 32-bit RISC-V MCUs with Internally Developed CPU Core
- Synopsys Adds AI-Driven Tools, Acquires PUF Security Firm
- Cycuity Sets New Standard for Semiconductor Chip Security Assurance with Next Generation of Radix Technology
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- SEMIFIVE Starts Mass Production of its 14nm AI Inference SoC Platform based Product
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
Most Popular
- Qualitas Semiconductor and Ambarella Sign Licensing Agreement
- ZeroPoint Technologies Signs Global Customer to Bring Hardware-Accelerated Compression to Hyperscale Data Centers
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- Intel and Arm Team Up to Power Startups
- Alphawave Semi and InnoLight Collaborate to Demonstrate Low Latency Linear Pluggable Optics with PCIe 6.0® Subsystem Solution for High-Performance AI Infrastructure at OFC 2024
E-mail This Article | Printer-Friendly Page |