Cadence X Architecture Design Solution Targets Nexsys(SM) ProcessSAN JOSE, Calif.--Oct. 4, 2005
--Taiwan Semiconductor Manufacturing Company (TSE:2330 - News; NYSE:TSM - News) today announced that it is ready to accept 90nm X Architecture designs.
The company has successfully qualified 90nm X Architecture design rules that can enable lower cost, higher performance and lower power designs. TSMC and Cadence Design Systems, Inc. have collaborated to validate the Cadence X Architecture design solution for the process. The two companies are now engaging mutual customers.
"TSMC and Cadence have worked collaboratively on the X Architecture for multiple process generations," said Ed Wan, senior director of product marketing for TSMC's design services division. "In each case, we have demonstrated tangible benefits in at least one of three critical areas: cost, performance or power, depending on the design."
Earlier this year, ATI Technologies Inc., Cadence and TSMC successfully produced the foundry industry's first X Architecture device -- a high-performance, high-volume PCI-Express graphics processor. ATI implemented the device using the Cadence X Architecture design solution and manufactured it on TSMC's 0.11-micron process. The design eliminated one metal layer, reducing the device's die cost.
Cadence and TSMC are members of the X Initiative, a semiconductor design chain consortium chartered with accelerating fabrication of the X Architecture. The X Architecture represents a new way of orienting a chip's microscopic interconnect wires with the pervasive use of diagonal routes, in addition to traditional right-angle "Manhattan" routing. The X Architecture can provide significant improvements in chip area, performance, power consumption and cost, by enabling designs with significantly less wirelength and fewer vias (the connectors between wiring layers).
"The combination of TSMC's advanced 90nm process technology and the Cadence X Architecture design solution provides a powerful way to optimize designs for today's challenging market needs," said Kalyan Thumaty, vice president and general manager of X Architecture at Cadence. "Working closely with TSMC and leading fabless semiconductor companies, we're helping the industry adopt the X Architecture and reap the benefits of this innovative approach."
The Cadence X Architecture design solution is the industry's first physical design solution that enables the pervasive use of diagonal routes and employs the familiar netlist-to-GDSII flow. While leveraging Cadence's industry-proven Manhattan implementation expertise, the solution draws on innovations in placement, routing, infrastructure and extraction technologies. Cadence X Architecture design solutions for TSMC's 0.13-micron, 0.11-micron, and 90-nm processes are now available to customers.About TSMC
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced twelve-inch wafer fabs, five eight-inch fabs and one six-inch wafer fab. TSMC also has substantial capacity commitments at its wholly-owned subsidiary, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC's corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com