UMC's Hu envisions new model for foundry business

Hu described an environment in which SoC design is becoming dauntingly difficult and crushingly expensive — $20 to 30 million for a tapeout, Hu estimated — and excess 8-inch wafer capacity has destroyed margins on mature processes. He added that foundries must be able to differentiate themselves through the cost-efficiency of advanced 12-inch processes and by their ability to provide IP to customers.

"Being a pure technology provider doesn't work any more," Hu said. "We have to make the transition from foundry to solutions provider." That means having the right IP, test and packaging capabilities along with wafer manufacturing expertise to turn customer designs into chips that function in-system.

"It also means system architecture expertise," Hu insisted.

Hu cited the collaboration among UMC, ARM, Artisan, National Semiconductor and Synopsys that led to the practical application of ARM's Intelligent Energy Management (IEM) architecture. Begun as a concept at ARM, IEM required UMC's process assistance, libraries from Artisan, external power-control chips from National and tools — many still under development — from Synopsys in order to move toward reality for chip designers.

Hu also cited an as-yet unannounced collaboration with Cadence Design Systems to provide a design environment, libraries and processes support for RF stages for ultrawideband CMOS radios. Hu did not elaborate.

Design for manufacturing (DFM) remains a major hurdle. "We can collect data from real silicon," Hu said. "This data can go into DFM-aware models of lithography and other process steps that designers can use before tapeout to identify potential problem areas. And it can feed DFM-aware tools to process data for optical proximity correction after tapeout. These are still very tough issues."

Meanwhile, the juggernaut of process development keeps rolling on. Hu claimed that UMC, having shipped over 100K "8-inch-equivalent wafers" in 90 nm, still leads the industry in shipments at that node. He admitted, however, that its lead might not last much longer.

With 65 nm barely out of prototype, Hu said he is already looking forward to 45 nm. UMC expects 45-nm wafers to ship in 2007 or 2008. "Which year it is will depend on when we receive delivery of the wet [immersion] scanners we need for the process," Hu said.

He also cited the process steps required for ultrashallow junctions and the accompanying millisecond anneal techniques as gating factors. He projected that neither high-k gate dielectric materials nor metal gates would be necessary until the 32 nm node.