Synopsys' Physical Compiler Enables Tape Out of Enterprise Server ASIC

MOUNTAIN VIEW, Calif.----Oct. 16, 2000--Synopsys, Inc. (Nasdaq:SNPS), today announced that Unisys Corporation has successfully used Physical Compiler, Synopsys' Physical Synthesis tool, to tape out a high-performance, 200 MHz, 1.5 million gate, 0.18 micron ASIC. Physical Compiler has now been adopted as a standard part of the Unisys ASIC design flow.

Before adopting Physical Compiler, the conventional Unisys back-end flow required intensive designer intervention resulting in design schedule unpredictability. Physical Compiler's unified synthesis and placement capability allowed Unisys to fix the last 1,000 timing violations in less than a week -- saving weeks of typical iterations.

``Timing closure is a significant challenge,'' said Wayne Engstrom, engineering director, Unisys Systems and Technology. ``With Physical Compiler, we saved several weeks of manual iteration on a very complex design. We have successfully inserted Synopsys' Physical Compiler into our standard ASIC design process, which includes Synopsys' Design Compiler and our ASIC vendor-supplied back-end tools.''

``We are extremely pleased at the success Unisys has achieved with Physical Compiler on one of their toughest designs,'' said Sanjiv Kaul, senior vice president and general manager for Synopsys' Physical Synthesis business unit. ``Tape outs are the true measure of success for an implementation tool. This tape out builds upon the success that Synopsys' Physical Synthesis has demonstrated through more than 25 tape outs of networking, communications, computing, and graphics chips.''

Synopsys' Physical Synthesis Solution

Pioneered by Synopsys, Physical Synthesis helps designers address the implementation challenges of next-generation system-on-chip designs. Physical Synthesis brings key physical design considerations to the front-end, allowing RTL designers to rapidly achieve high quality of results. The overall design flow includes Chip Architect design planner, Physical Compiler unified synthesis and placement, and FlexRoute top-level router. Synopsys' Physical Synthesis leverages industry-standard tools such as Design Compiler(TM), Module Compiler(TM) and PrimeTime® and its proven interfaces to third-party solutions allow it to easily plug into an existing design flow.

Pricing and Availability

Physical Compiler is available now. Pricing for a single-user, one-year term license begins at $100,000. Support and maintenance options vary and are in addition to the product license.

About Unisys

Unisys is an e-business solutions company whose 36,000 employees help customers in 100 countries apply information technology to seize opportunities and overcome challenges of the Internet economy. Unisys people integrate and deliver the solutions, services, platforms and network infrastructure required by business and government to transform their organizations for success in this new era. The company offers a rich portfolio of Unisys e-@ction Solutions for e-business based on its expertise in vertical industry solutions, network services, outsourcing, systems integration and multivendor support, coupled with enterprise-class server and related technologies. The primary vertical markets Unisys serves worldwide include financial services, transportation, communications, publishing and commercial sectors, as well as the public sector, including federal government customers. Unisys is headquartered in Blue Bell, Pennsylvania, in the Greater Philadelphia area. For more information on the company, access the Unisys home page on the World Wide Web at http://www.unisys.com.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.

Synopsys and PrimeTime are registered trademarks of Synopsys, Inc. Design Compiler and Module Compiler are trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

Contact:

     Synopsys, Inc.       Robert Smith, 650/584-1261       rsmith@synopsys.com          or       KVO Public Relations       Bill Warner, 503/402-1449       bill_warner@kvo.com