SANTA CLARA, Calif. -- Improv Systems Inc. this week unveiled its first "off-the-shelf" application platform for highly integrated chips aimed at performing voice codec and echo cancellation functions in voice-over-packet (VoP) networking equipment.
Based on the startup's Jazz processor and Programmable System Architecture (see March 6 story), the Acappella platform is being licensed to chip suppliers and system houses for custom and standard ICs used in VoP applications in the home and office. According to Improv, the Acappella offers a complete package of capabilities for products requiring high-performance, high-channel density packetized voice and echo cancellation processing.
Initially three platforms are being aimed at three market segments. The Acappella Home is targeted at home access systems with support for four channels running a number of ITU codecs along with G.16 8 echo cancellation. A platform for integrated access device applications in offices supports 16 to 32 channels for a standalone and integrated solution. And a gateway platform for 180 voice or 120 echo channels per chip is also being offered.
For the gateway application, the platform cuts the amount of chips needed for the solution to less than half the number of general-purpose digital signal processors, according to Improv.
"This is the first of several platform solutions that are being lined up for the next several months," said Bob Bell, director of applications at the Santa Clara company.
The "chipless" semiconductor company has announced two Programmable Systems Architecture (PSA) licensees--with Philips Semiconductors and STMicroelectronics--and more are in the works, said Bell in an interview with SBN. Improv has also struck a partnership with Kawasaki Semiconductor, which plans to offer products based on the Acappella platforms implemented in its 0.18-micron technology.
Durin g the summer, Improv signed a licensing pact with its the systems company--TeleHubLink Corp. The Burlington, Mass., company is using Improv's Jazz multiprocessor platform for wireless encryption systems.
In the integrated access device (IAD) office segment, the Acappella will pack two Jazz very long instruction word (VLIW) processors on a chip along with 25 kilobytes of shared memory in a space of 25 mm2 using a 0.18-micron process technology. The average power consumption of this 100-MHz platform will be 580 mW, said Improv.
The one-processor Acappella Home platform will have average power consumption of 315 mW operating at 10 MHz. The gateway platform with four Jazz VLIW processors will take up 100 mm2 and have an average power consumption of 1,785 mW operating at 150 MHz.
By the third quarter of 2001, Improv plans to offer a third-generation Acappella VoP platform that operates at 200 MHz and integrates more function on chip. "The trend going forward is for more integrati on. We plan to bring the embedded microcontroller into the system-on-chip design," Bell explained. "We will also pull in some of the functionality, such as the high-level telephony protocol stacks."