Best practices for structured-ASIC design
EE Times: Best practices for structured-ASIC design | |
Frank McMillan (10/17/2005 10:00 AM EDT) URL: http://www.eetimes.com/showArticle.jhtml?articleID=172300906 | |
Given the increasing nonrecurring engineering charges and long design schedules associated with deep-submicron standard-cell ASICs, the use of structured ASICs for custom IC design is an increasingly attractive option. Structured ASICs offer good silicon performance at competitive unit cost, with much lower NREs. The wide range of sizes available for the structured ASIC means it can be used either as the main system chip or as a small, cost- effective side chip. Many physical design issues are already addressed in the structured-ASIC slice design, so the time taken for the back-end layout work can be reduced, leading to quicker signoff and prototype delivery. But the ASIC slices have a predefined structure, so the designer must carefully consider arrangement of chip resources to achieve the desired performance. FPGAs offer another alternative to ASICs. They are usually based on lookup tables and configurable logic cells, and they are less area-efficient and more power-hungry than comparable ASIC technologies. Once annual production volumes move above 5,000 pieces, it is often much more cost-effective to use a structured ASIC. Still, in many applications, FPGAs serve as an ideal prototyping tool, providing quick turnaround with low up-front cost. If the design is prototyped in an FPGA, it is important to plan for migration to the chosen structured ASIC. Ideally, co-development using FPGA and ASIC libraries can be done early on. But even without that, a little planning can make the migration fairly painless. Do
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Frank McMillan (frankm@chipx.com), senior applications engineer at ChipX (Northampton, England) See related chart
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