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USB V3.1 Power Delivery Type-C Port Evaluation board for OTI9108 IP
Digital Core Design (DCD) Announces New Configurable CAN Bus Controller
October 18, 2005 – The Intellectual Property (IP) provider - Digital Core Design (DCD) today has announced the release of the DCAN – Configurable CAN Bus Controller IP Core.
The DCAN is a stand-alone controller for the Controller Area Network (CAN) widely used in automotive and industrial applications. DCAN conforms to Bosch CAN 2.0B specification (2.0B Active). Core has simple configurable CPU interface which allows to operate with 8, 16 and 32 Bit CPU with little endian or big endian adressing scheme. DCAN supports both standard (11 bit identifier) and extended (29 bit identifier) frames. Hardware message filtering and 64 byte receive FIFO enables back-to-back message reception with minimum CPU load. The DCAN is designed in pure HDL languages allowing targeting in FPGA or ASIC technologies.
The Customer can select VHDL/Verilog source code or FPGA Netlists. IP Core is licensed under Single Design or Unlimited Designs options. If you have any questions, please feel free to contact DCD. http://www.dcd.pl/acontact.php
For more information about this product please check:
DCAN – Configurable CAN Controller
About Digital Core Design
Digital Core Design (DCD) is a private Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house, an expert in IP cores architecture improvements. DCD sells its products and services directly and through its global distribution network. DCD offers VHDL and Verilog high performance and synthesizable IP cores for a speed optimized 8-, 16- and 32-bit processors, peripherals, serial interfaces, floating point arithmetic units and coprocessors. The functionality of IP solutions offered by DCD were up to date appreciated by over 200 licenses sold to over 150 customers worldwide, such as: INTEL, SIEMENS, PHILIPS, TOYOTA, MAXIM, RAYTHEON, OSRAM, GENERAL ELECTRIC, FARADAY, SAGEM, FLEXTRONICS and GOODRICH. DCD also became a member of first-class branch partner programs like: AMPP of ALTERA, AllianceCORE of XILINX, ispLeverCORE Connection of LATTICE and IP Catalyst of SYNOPSYS. For more information, please visit: http://www.dcd.pl.
The DCAN is a stand-alone controller for the Controller Area Network (CAN) widely used in automotive and industrial applications. DCAN conforms to Bosch CAN 2.0B specification (2.0B Active). Core has simple configurable CPU interface which allows to operate with 8, 16 and 32 Bit CPU with little endian or big endian adressing scheme. DCAN supports both standard (11 bit identifier) and extended (29 bit identifier) frames. Hardware message filtering and 64 byte receive FIFO enables back-to-back message reception with minimum CPU load. The DCAN is designed in pure HDL languages allowing targeting in FPGA or ASIC technologies.
The Customer can select VHDL/Verilog source code or FPGA Netlists. IP Core is licensed under Single Design or Unlimited Designs options. If you have any questions, please feel free to contact DCD. http://www.dcd.pl/acontact.php
For more information about this product please check:
DCAN – Configurable CAN Controller
About Digital Core Design
Digital Core Design (DCD) is a private Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house, an expert in IP cores architecture improvements. DCD sells its products and services directly and through its global distribution network. DCD offers VHDL and Verilog high performance and synthesizable IP cores for a speed optimized 8-, 16- and 32-bit processors, peripherals, serial interfaces, floating point arithmetic units and coprocessors. The functionality of IP solutions offered by DCD were up to date appreciated by over 200 licenses sold to over 150 customers worldwide, such as: INTEL, SIEMENS, PHILIPS, TOYOTA, MAXIM, RAYTHEON, OSRAM, GENERAL ELECTRIC, FARADAY, SAGEM, FLEXTRONICS and GOODRICH. DCD also became a member of first-class branch partner programs like: AMPP of ALTERA, AllianceCORE of XILINX, ispLeverCORE Connection of LATTICE and IP Catalyst of SYNOPSYS. For more information, please visit: http://www.dcd.pl.
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