SAN JOSE, Calif., Oct 19, 2005
-- SynTest Technologies, Inc., a leading supplier of Design-for-Test (DFT) tools, was granted 33 claims on Oct. 11, 2005 under United States Patent # 6,954,887 for its invention of at-speed testing of asynchronous multi-clock, multi-frequency designs, using ATPG or Logic BIST DFT schemes.
The patented invention is in general referred to as "staggered skewed-load" or "staggered launch-on-shift". It is a method for providing true at-speed testing for synchronous and asynchronous multi-clock, multi-frequency domains. The method provides ordered capture clocks to detect or locate faults within multiple clock domains and faults crossing clock domains in an integrated circuit during at-speed BIST or at-speed scan-testing.
The major benefit of this patented DFT scheme is the reduction in the number of ATPG patterns compared to the traditional one-hot DFT scheme for multi-clock, multi-frequency designs. The resultant compaction of 3x-10x translates directly into test cost savings.
SynTest Technologies, Inc., established in 1990, develops IPs for advanced design-for-test (DFT) and design-for-debug/diagnosis (DFD) applications and markets them throughout the world, to semiconductor companies, system houses and design service providers. The company has filed more than 20 US patents. The Company's products improve an electronic design's quality and reduce overall design and test costs. Various applications that use these IPs include logic BIST, memory BIST, boundary-scan synthesis, Scan/ATPG with test compression, concurrent fault simulation, silicon debug and diagnosis. The company headquartered in Sunnyvale, California, has offices in China, Taiwan, Korea and Japan, and distributors in Europe and Asia including Israel. More information is available at www.syntest.com.