P.A. Semi Unveils Game-Changing Multicore Processor Family

Industry Veterans Launch New Company and PWRficient^TM Processor Family; Announce Power Architecture^TM License from IBM.

Fall Processor Forum – San Jose, Calif. – Oct. 24, 2005 – Emerging from more than two years of stealth development, P.A. Semi today unveiled the PWRficient^TM processor family—a 64-bit multicore, scalable processor line based on the Power Architecture^TM from IBM—that delivers high performance at very low power consumption, offering up to a tenfold advantage in performance per watt over the industry. P.A. Semi is headed by Dan Dobberpuhl, the acclaimed lead designer of the DEC Alpha series of microprocessors, the ultra-power-efficient StrongARM microprocessors, and the first commercial multicore processors including the SiByte 1250. The 150-strong processor, ASIC, software and systems engineering team also includes key designers of other defining processor architectures, such as Opteron, Itanium, and UltraSPARC.

"The next wave of microprocessor innovation is contingent on solving the problem of dramatically increased power consumption," said cofounder, president, and CEO Dan Dobberpuhl. "We had to start from scratch, rethinking every step, to achieve our breakthrough performance-per-watt design. The result is a paradigm-shifting processor that has been enthusiastically received by our customers, who look forward to building a new breed of cool, efficient, yet high-performance, systems around the PWRficient processor."

PWRficient HIGH PERFORMANCE AT LOW POWER

The PWRficient processors address the multibillion-dollar high-performance embedded and computing markets to redefine power, cost, and throughput efficiency in high-performance processing. The unique system-on-chip architecture and design, underpinned by 50 patents filed and pending, delivers high performance (up to 2.5GHz per-core) at phenomenally low power consumption. In terms of performance per watt, the defining metric for all next- generation processors, PWRficient is up to 10 times superior to the competition. For example, the first PWRficient processor, a dual-core chip running at 2GHz, dissipates just 5-13 watts typical, depending upon the application.

Beyond performance per watt, the PWRficient processor delivers key breakthroughs in cost and throughput efficiency. PWRficient processors are the first processors in their class to integrate what is typically a three- to five-chip-set platform into a single chip, called a "platform processor." Not only does the integration of the cores, memory, south bridge, and high-speed I/O onto one chip dramatically reduce the cost of silicon and power consumption, but it also delivers high throughput at low latency.

PWRficient SCALABILITY

Through its unique modular architecture, which allows the number of cores, memory controllers, cache, serdes lanes, and protocols to easily scale, P.A. Semi will deliver a family of PWRficient processors targeting a variety of applications, including high-performance computing, embedded datacom and telecom, storage, and other embedded consumer applications. Additionally, this modularity advantage enables P.A. Semi to tape out new PWRficient processors in one quarter, versus the years common in the industry

"P.A. Semi's PWRficient processor addresses the fundamental challenge facing all next-generation processors by delivering higher performance and reduced power," says In-Stat analyst and Microprocessor Report editor in chief Kevin Krewell. "In being phenomenally low-power while still being able to run at high clock speeds, the PWRficient processor is ahead of today's processors and will be a significant challenger to the much vaunted devices on its competitors' roadmaps."

THE PWRficient PROCESSOR ROLLOUT

The first PWRficient chip, the PA6T-1682M, which dissipates between just 5-13 watts, depending upon the application, is a dual-core implementation running at 2GHz with two DDR2 memory controllers, 2MB of L2 cache, and a flexible I/O subsystem that supports eight PCI Express controllers, two 10 Gigabit Ethernet XAUI controllers, and four Gigabit Ethernet SGMII controllers sharing 24 serdes lanes. It will sample in the third calendar quarter of 2006, with single-core and quad-core versions due in early and late 2007, respectively, and an eight-core version planned for 2008.

PWRficient ARCHITECTURAL ELEMENTS

The PWRficient family of platform processors is derived from a common set of fundamental architectural elements. A coherent, ordered crossbar called CONEXIUMTM interconnects multiple Power cores, L2 caches, memory controllers, and the ENVOITM I/O subsystem. ENVOI combines a set of configurable serdes lanes with a set of protocol controllers for such I/O standards as PCI Express, Gigabit Ethernet, and 10 Gigabit Ethernet.

These controllers share a bridge to CONEXIUM, as well as a set of centralized DMA channels, offload engines, and a coherent I/O cache. The architecture supports a variety of offload engines, including support for TCP/IP, iSCSI, cryptography (IPSec and SSL), and RAID. This layered, scalable architecture results in versatile single-chip solutions that can be quickly developed by combining the appropriate number of Power cores, memory controllers, and L2 caches with a suitable number of serdes lanes and protocol controllers.

P.A. Semi also employs a unique scalable-socket plan, which provides several options for performance upgrades or cost reductions with little or no design effort. P. A. Semi defines a "socket" (package, pinout, and power envelope) by the number of memory controllers (up to four), the number of serdes I/O lanes (up to 32), and the supported system peripherals. Each socket supports several performance levels by varying the number of cores (up to eight on a chip) and the size of the L2 cache (up to 8MB). Within a socket definition, processors are tailored to different applications by adjusting the number and type of the high-speed I/O protocols (for example PCI Express, 10 Gigabit Ethernet, 1 Gigabit Ethernet, SATA/SAS, RapidIO, and Fibre Channel). Initial socket definitions include the "E" socket (entry), "M" socket (midrange), and "P" socket (performance). Customers can design to a specific socket, instead of a specific processor, to enable easy migration to compatible processors.

P.A. SEMI STRATEGIC PARTNERS AND ECOSYSTEM

P.A. Semi is partnered with some of the most notable names in technology, having licensed the Power Architecture from IBM [see other news release, P.A. Semi Signs Power Architecture License], and is supported by an ecosystem of partners, including Macraigor Systems, Micron, MontaVista Software, QNX Software Systems, SMART Modular Technologies, Inc., Terra Soft Solutions, and Wind River.

P.A. Semi is backed by two of the most respected venture-capital firms, Bessemer Venture Partners and Venrock Associates.

FALL PROCESSOR FORUM PRESENTATION

Jim Keller, vice president of engineering, Architecture Group, P.A. Semi, will present the PWRficient processor architecture at Fall Processor Forum in San Jose, California, on Tuesday, October 25 at 9:50 a.m. in a session titled "A Power-Efficient, Scalable Processor Family." The new PWRficient processor will also be demonstrated at the show on an EVE (Emulation and Verification Engineering) ZeBu-XL emulation platform.

More information on P.A. Semi, its founders, the PWRficient processor family, and its partners appears on the new P.A. Semi web site, also launched today, at www.pasemi.com.