The SPEAr Head Configurable System on Chip IC Offers an Advanced ARM Architecture, and Advanced Features, as Well as the Set of Peripherals and Bank of Configurable Logic Confirming Unprecedented Flexibility and Time to Market for Most Applications
GENEVA, Oct. 24, 2005 -- STMicroelectronics (NYSE: STM), a worldwide leader in system-on-chip technology, revealed today the successful validation and release of SPEAr Head, a new member of the company's SPEAr (Structured Processor Enhanced Architecture) family of configurable System-on-Chip ICs that address a variety of applications, including digital engines for printers, scanners and other embedded control applications, providing ST customers with a complete roadmap that covers current and future needs.
The new SPEAr Head (part number SPEAr-09-H020) integrates an advanced ARM926EJ-S core running at 266MHz, a complete set of IP (intellectual property) blocks and a configurable logic block that allows an incomparable level of flexibility in high-complexity system implementation. The new device makes it possible to achieve extremely fast customization of critical functions in a fraction of the time and cost required by a full-custom design approach.
"With this new chip introduction, ST has confirmed its commitment to the SPEAr family and its roadmap," said Vittorio Peduto, General Manager of ST's Computer Systems Division. "ST continues to deliver SoCs that have a proven and tested architecture and offer state-of-the-art processor cores, technology and sophisticated IP, thereby minimizing customer investment and allowing them to leverage their core competences, which can be easily customized in the SPEAr family's configurable logic element, as if it was a fully custom device. Specific IP, such as a dithered PLL, special I/Os to minimize on-board reflections, automatically reconfigurable DDR/SDRAM interface and a distributed DMA architecture make this chip unique in the market."
The new device includes: an ARM926EJ-S running at 266MHz with 32 Kbytes of Instruction cache, 16 Kbytes of Data cache, 8-Kbyte Data-TCM (Tightly Coupled Memory) and 8-Kbyte Instruction-TCM, and three USB2.0 ports (two hosts and one device supporting high speed mode); an Ethernet 10/100 MAC; a 16-channel 8-bit A/D converter; an I2C interface; three UARTs; SDRAM memory interfaces at 133MHz supporting DDR and SDR; SPI interface supporting serial FLASH/ROM; one full USB-dedicated PLL and one dithered system PLL; and 200-kgate (ASIC equivalent) of configurable logic connected to four banks of 4 KBytes SRAM each. A Real Time Clock, Watchdog and four general-purpose timers complete the SoC structure. Additionally, the device supports a wide range of operating systems, including Linux, Nucleus, uItron, and Vxworks.
Samples of SPEAr Head are already available, with pricing in the range of $12 in volume quantities. Full development boards will be shipped in December. A special dual-mode development environment has been implemented to allow ST customers either to use an ASIC-like approach to design their custom logic or to develop their solution with an external FPGA, verify the solution and finally map it into the configurable logic.
STMicroelectronics is a global leader in developing and delivering semiconductor solutions across the spectrum of microelectronics applications. An unrivalled combination of silicon and system expertise, manufacturing strength, Intellectual Property (IP) portfolio and strategic partners positions the Company at the forefront of System-on-Chip (SoC) technology and its products play a key role in enabling today's convergence markets. The Company's shares are traded on the New York Stock Exchange, on Euronext Paris and on the Milan Stock Exchange. In 2004, the Company's net revenues were $8.76 billion and net earnings were $601 million. Further information on ST can be found at http://www.st.com.