CAMPBELL, Calif., 25th October, 2005 - Silicon Interfaces, a high-end design services and leading provider for IP’s in Europe, North America and Asia-Pacific, under their IP Development Program - Silicon Cores: Core to the Intelligent Systems™, today announced the availability of USB 2.0 RVM VIP (Reference Verification Methodology), (Verification) intellectual property (VIP). The SI60USBRVM10, USB 2.0 RVM VIP increases the portfolio of Silicon Interfaces Verification IP’s.
Silicon Interfaces’ USB 2.0 Vera RVM VIP is fully documented, off the shelf component for the Verification of the USB 2.0 compliant function controller. USB 2.0 Vera RVM VIP provides a concise, declarative mechanism to verify USB 2.0 Function Controller.
This VIP is developed using the Synopsys’ Vera Reuse Verification Methodology that is used in dynamic simulation of USB 2.0 based design.
The RVM methodology is based on the following cornerstones:
- Constrained random stimulus generation raises the abstraction level in test bench code
- DFV improves the observability of design errors by providing means for an abstract specification of the Device behavior using assertions
- Reusable test benches and reusable assertion-based checkers reduce the effort needed to verify complex Devices and interface protocols
The objective of RVM methodology is to create a test environment with the following characteristics or features:
- Use functional coverage metrics to direct the verification effort and measure progress
- Maximum use of random stimulus
- Creation and use of reusable verification components
- Portability across various levels of abstraction of the DUT
- Portability from block-level to system-level
The VIP provides a fast, accurate way to simplify and speed-up the device verification task in a complex design process, verification can take up to 70% of the development time.
USB 2.0 Vera RVM VIP speeds up the verification process providing a compelling cost and time to market, said Pervez Bharucha, Chief Technical Consultant for Synopsys verification technologies at Silicon Interfaces. Object Oriented Programming approach plays one of the key roles to achieve these goals. Writing a reusable code makes it easy for the Verification Engineer to apply the same tasks in various modules from project-to-project and code is maintainable.
SI60USBRVM10, USB 2.0 RVM VIP Specifications
- The VIP can work with 8-bit or 16-bit standard USB devices
- Error Injection Mechanism, which can be turned ON or OFF for a given simulation run. Incorporated around 45+ scenarios for different Error types.
- Provides a choice for RESETTING to either High-Speed or Full-Speed mode upon startup
- Supports RESET/SUSPEND/RESUME. On-the-fly Reset switch over from High-Speed to Full-Speed or vice-versa supported
For a complete listing of features and pricing of SI60USBRVM10, USB 2.0 RVM VIP, please visit the Silicon Cores web site at http://www.siliconcores.com
The SI60USBRVM10, USB 2.0 RVM VIP is available now
USB 2.0 Vera RVM VIP can work in a standalone mode i.e. can be plugged with any Function Controller with standard pin outs without disturbing the structure.
About Silicon Interfaces
Silicon Interfaces has experience in verification solutions and developing IP for Fabric Channel Interconnect, Telecom and Networking domains, including Bluetooth Baseband, Gigabit Ethernet MAC, SONET Framer STS-1/3, 1394, USB2 Function Controller, USB On-The-Go, Infiniband, 8530, 8051, 7990, UART, Rapid IO and 802.11 a/b/g MAC. Currently, our Roadmap IPs is PCI-Express, 10 Giga and SONET STS Framer–12. The IP has had considerable maturity based on certification, targets to various FPGA devices and ASIC libraries, silicon area optimization, silicon prototyping, testing and validation. Also available are OVA AIP like Bluetooth Baseband OVA AIP, USB 2.0, OVA AIP and Gigabit OVA as well as RapidIO VIP. We have an extensive driver development program in order to offer a packaged solution to the customer. For more information please visit http://www.siliconcores.com